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broadband modem mixed-signal front end AD9865 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures l o w c o st 3.3 v cmos mxfe tm f o r br oadband modems 10-bit d/a c o n v er t e r 2/4 int e rpola t ion filt er 200 msps d a c upda t e r a t e int e gr a t ed 23 dbm line dri v er with 19.5 db g a in c o ntrol 10-bit , 80 msp s a/d c o n v er te r ?12 db to +48 db low no ise rxpga (< 3.0 nv /r thz) t h ir d or der , progr a mmable lo w - pass filt er f l e x ible digita l da ta pa th in t e r f ac e half- and f u ll - d uple x oper a t ion backward- c ompa tible with a d 9975 and ad 9875 v a rious pow e r- down/r educ tion modes in t e rnal clock mu ltiplier (pll) 2 auxili ar y pr ogr a mmable clock outputs a v ai lable in 64 -lead chip sc ale pack age or bar e die applic a t io ns p o w e rline net w ork i ng vdsl and hpn a func ti on a l bl ock di a g r a m 10 xt a l rx ? 4 6 a d 9865 10 0 to ?7.5db 04493- 0- 001 0 to ?12db register control clk syn. adc 80msps 2-4x iou t _ g + iou t _ n + iou t _ n ? iou t _ g ? cl k o ut _1 cl k o ut _2 os c i n rx + iamp txdac iout _p+ iout _p ? 2 m clk multiplier 2-pole lpf 1-pole lpf 0 to 6db ? = 1db ? 6 to 18db ? = 6db ?6 to 24db ? = 6db spi ag c [ 5: 0] rx cl k r xe/ syn c a d i o [9 :4 ]/ t x [5 :0 ] a d i o [3 :0 ]/ r x [5 :0 ] tx c l k t xen / syn c mo d e pw r d w n fi g u r e 1 . gener a l description the AD9865 is a mixed-sig n al f r o n t end (mxfe) i c f o r t r a n s c ei v e r a p pl ica t io n s r e q u ir i n g tx an d rx p a t h f u n c t i o n a l i t y w i t h d a t a r a te s up to 8 0 m s p s . i t s f l e x ibl e d i g i t a l i n te r f a c e, p o w e r s a v i n g mo des, an d hig h tx -to - rx is ola t i o n ma k e i t wel l s u i t e d f o r half- a nd f u l l -d u p lex a p p l ic a t io n s . the dig i tal in t e r - face is extr eme l y f l exi b le al lo win g sim p le in t e r f aces t o dig i tal bac k e n ds tha t su p p o r t half- o r f u l l -d u p lex da t a tra n sfers, th us o f t e n al lo win g t h e AD9865 t o rep l ace dis c r e te ad c an d d a c so l u ti o n s . p o w e r sa vi n g m o d e s i n c l u d e t h e a b il i t y t o r e d u c e p o we r c o nsu m pt i o n of i n d i v i du a l f u nc t i on a l bl o c k s , or to p o w e r do wn u n us e d b l o c ks in half-d u p lex a p p l ica t io ns. a s e r i al p o r t in t e r f ace (s pi ? ) a l lo ws s o f t wa r e p r og ra mmin g o f t h e v a r i o u s fun c ti o n al b l ock s . a n o n - c hi p p ll c l oc k m u l t i p li er a n d sy n t h e si zer p r o v id e a l l t h e r e q u ir e d i n t e r n a l clo c ks, as wel l as tw o ext e r n a l clo c ks f r o m a sin g l e cr y s t a l o r clo c k s o ur ce. t h e t x s i gnal pa th c o n s i s t s o f a b y pa s s a b l e 2 /4 l o w - pa s s in ter p ol a t ion f i l t er , a 10- b i t tx d a c, and a li ne dr i v er . t h e t r a n smi t p a t h si g n a l b a n d wi d t h ca n b e as h i g h as 34 mh z a t an in p u t da t a ra te o f 80 ms ps. the txd a c p r o v i d es dif f er en t i al c u r r en t o u t p u t s tha t c a n be st eer ed dir e c t l y t o an ext e r n al lo ad or to an i n te r n a l l o w d i s t or t i on c u r r e n t am pl i f i e r . t h e c u r r e n t a m plif ier (i am p) ca n b e co nf ig ur e d as a c u r r en t- o r v o l t a g e- m o de li ne dr i v e r (wi t h t w o ex te r n a l n p n t r an sisto r s) ca p a b l e o f de liv e r i n g in exces s o f 23 db m p e ak s i g n al p o wer . tx p o w e r can be dig i tal l y co n t r o l l ed o v er a 19.5 db ra n g e in 0. 5 db s t eps. the r e cei v e p a t h co n s is ts o f a pr og ra mma b l e a m plif ier (rxpga), a t u na b l e lo w-p a s s f i l t er (lp f ), a nd a 10-b i t ad c. the lo w n o is e r x pga has a p r og ra mma b l e ga in ra n g e o f ?12 db t o +48 db in 1 db s t eps. i t s in p u t r e f e r r ed n o is e is les s tha n 3 nv/r th z f o r ga in s e t t in gs beyon d 36 db . the r e cei v e p a t h lp f c u t o f f f r eq uen c y ca n be s e t o v er a 15 mh z t o 35 mh z ra n g e o r sim p l y b y p a s s e d . the 10-b i t ad c achi e v es exce l l en t d y na mic p e r f o r ma n c e o v er a 5 ms ps t o 80 ms ps s p a n . b o t h th e r x pga a n d th e a d c o f f e r sca l a b le po w e r co n s um p t i o n a l l o w i ng p o we r / p e r f or m a nc e o p t i m i z a t i on . the AD9865 p r o v ides a hig h l y in t e g r a t e d s o l u tio n f o r ma n y b r o a d b and m o d e m s . i t is a v a i l a b l e in a sp ac e s a vi n g 64-p i n ch i p s c ale p a cka g e and is s p e c if ie d o v er t h e comm er cial (?40c t o +85c) t e m p era t ur e ra n g e .
AD9865 rev. a | page 2 of 48 table of contents specifications ..................................................................................... 3 tx path specifications .................................................................. 3 rx path specifications .................................................................. 4 power supply specifications ....................................................... 5 digital specifications ................................................................... 6 serial port timing specifications ............................................... 7 half-duplex data interface (adio port) timing specifications ................................................................................ 7 full-duplex data interface (tx and rx port) timing specifications ................................................................................ 8 explanation of test levels ........................................................... 8 absolute maximum ratings ............................................................ 9 thermal characteristics .............................................................. 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 rx path typical performance characteristics ........................ 12 txdac path typical performance characteristics ............... 16 iamp path typical performance characteristics .................. 18 serial port ........................................................................................ 19 register map description ......................................................... 21 serial port interface (spi) ......................................................... 21 digital interface .............................................................................. 23 half-duplex mode ..................................................................... 23 full-duplex mode ...................................................................... 24 rxpga control .......................................................................... 25 txpga control .......................................................................... 27 transmit path .................................................................................. 28 digital interpolation filters ...................................................... 28 txdac and iamp architecture .............................................. 28 tx programmable gain control .............................................. 30 txdac output operation ........................................................ 30 iamp current-mode operation .............................................. 30 iamp voltage-mode operation .............................................. 31 iamp current consumption considerations ........................ 32 receive path .................................................................................... 33 rx programmable gain amplifier ........................................... 33 low-pass filter ........................................................................... 34 analog-to-digital converter (adc) ....................................... 35 agc timing considerations .................................................... 36 clock synthesizer ........................................................................... 37 power control and dissipation .................................................... 39 power-down ............................................................................... 39 half-duplex power savings ...................................................... 39 power reduction options ......................................................... 40 power dissipation ...................................................................... 42 mode select upon power-up and reset .................................. 42 analog and digital loop-back test modes ............................ 43 pcb design considerations .......................................................... 44 component placement .............................................................. 44 power planes and decoupling .................................................. 44 ground planes ............................................................................ 44 signal routing ............................................................................ 44 evaluation board ............................................................................ 46 outline dimensions ....................................................................... 47 ordering guide .......................................................................... 47 revision history 11/04data sheet changed from rev. 0 to rev. a changes to specifications tables .................................................... 3 changes to serial table .................................................................. 19 changes to full duplex mode section......................................... 24 change to txdac and iamp architecture section .................. 29 change to txdac output operation section............................ 30 insert equation................................................................................ 37 change to figure 84 caption ......................................................... 42 11/03revision 0: initial version
AD9865 rev. a | page 3 of 48 specifications tx path specifications avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%; f oscin = 50 mhz, f dac = 200 mhz, r set = 2.0 k?, unless otherwise noted. table 1. parameter temp test level min typ max unit txdac dc characteristics resolution full 10 bits update rate full ii 200 msps full-scale output current (ioutp_fs) full iv 2 25 ma gain error 1 25c i 2 % fs offset error 25c v 2 a voltage compliance range full ?1 +1.5 v txdac gain control characteristics minimum gain 25c v ?7.5 db maximum gain 25c v 0 db gain step size 25c v 0.5 db gain step accuracy 25c iv monotonic gain range error 25c v 2 db txdac ac characteristics 2 fundamental 0.5 dbm signal-to-noise and distortion (sinad) full iv 62.0 63.1 dbc signal-to-noise ratio (snr) full iv 62.5 63.2 dbc total harmonic distortion (thd) full iv ?77.7 ?67.0 dbc spurious-free dynamic range (sfdr) full iv 67.1 79.3 dbc iamp dc characteristics ioutn full-scale current = ioutn+ + ioutn? full iv 2 105 ma ioutg full-scale current = ioutg+ + ioutg? full iv 2 150 ma ac voltage compliance range full iv 1 7 v iampn ac characteristics 3 fundamental 25c 13 dbm ioutn sfdr (third harmonic) full iv 43.3 45.2 dbc iamp gain control characteristics minimum gain 25c v ?19.5 db maximum gain 25c v 0 db gain step size 25c v 0.5 db gain step accuracy 25c iv monotonic db ioutn gain range error 25c v 0.5 db reference internal reference voltage 4 25c i 1.23 v reference error full v 0.7 3.4 % reference drift full v 30 ppm/ o c tx digital filter characteristics (2 interpolation) latency (relative to 1/f dac ) full v 43 cycles ?0.2 db bandwidth full v 0.2187 f out /f dac ?3 db bandwidth full v 0.2405 f out /f dac stop-band rejection (0.289 f dac to 0.711 f dac ) full v 50 db
AD9865 rev. a | page 4 of 48 parameter temp test level min typ max unit tx digital filter characteristics (4 interpolation) latency (relative to 1/ f dac ) full v 96 cycles ?0.2 db bandwidth full v 0.1095 f out /f dac ?3 db bandwidth full v 0.1202 f out /f dac stop band rejection (0.289 f oscin to 0.711 f oscin ) full v 50 db pll clk multiplier oscin frequency range full iv 5 80 mhz internal vco frequency range full iv 20 200 mhz duty cycle full ii 40 60 % oscin impedance 25c v 100//3 ?/pf clkout1 jitter 5 25c iii 12 ps rms clkout2 jitter 6 25c iii 6 ps rms clkout1 and clkout2 duty cycle 7 full iii 45 55 % 1 gain error and gain temperature coefficients are based on the adc only (with a fixed 1.23 v external reference and a 1 v p-p differential analog input). 2 txdac ioutfs = 20 ma, differential output with 1:1 transformer with source and load termination of 50 ?, f out = 5 mhz, 4x interpolation. 3 ioun full-scale current = 80 ma, f oscin = 80 mhz, f dac =160 mhz, 2x interpolation. 4 use external amplifier to drive additional load. 5 internal vco operates at 200 mhz , set to divide-by - 1. 6 because clkout2 is a divided down version of oscin, its jitter is typically equal to oscin. 7 clkout2 is an inverted replica of oscin, if set to divide-by-1. rx path specifications avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%; half- or full-duplex operation with config = 0 default power bias settings, unless otherwise noted. table 2. parameter temp test level min typ max unit rx input characteristics input voltage span (rxpga gain = ?10 db) full iii 6.33 v p-p input voltage span (rxpga gain = +48 db) full iii 8 mv p-p input common-mode voltage 25c iii 1.3 v differential input impedance 25c iii 400 4.0 ? pf input bandwidth (with rxlpf disabled, rxpga = 0 db) 25c iii 53 mhz input voltage noise density (rxpga gain = 36 db, f ?3 dbf = 26 mhz) 25c iii 3.0 nv/rthz input voltage noise density (rxpga gain = 48 db, f ?3 dbf = 26 mhz) 25c iii 2.4 nv/rthz rxpga characteristics minimum gain 25c iii ?12 db maximum gain 25c iii 48 db gain step size 25c iii 1 db gain step accuracy 25c iii monotonic db gain range error 25c iii 0.5 db rxlpf characteristics cutoff frequency (f ?3 dbf ) range full iii 15 35 mhz attenuation at 55.2 mhz with f ?3 dbf = 21 mhz 25c iii 20 db pass-band ripple 25c iii 1 db settling time to 5 db rxpga gain step @ f adc = 50 msps 25c iii 20 ns settling time to 60 db rxpga gain step @ f adc = 50 msps 25c iii 100 ns adc dc characteristics resolution na na 10 bits conversion rate full ii 5 80 msps
AD9865 rev. a | page 5 of 48 parameter temp test level min typ max unit rx path latency 1 full-duplex interface full v 10.5 cycles half-duplex interface full v 10.0 cycles rx path composite ac performance @ f adc = 50 msps 2 rxpga gain = 48 db (full-scale = 8.0 mv p-p) signal-to-noise and distortion (snr) 25c iii 43.7 dbc total harmonic distortion (thd) 25c iii ?71 dbc rxpga gain = 24 db (full-scale =126 mv p-p) signal-to-noise (snr) 25c iii 59 dbc total harmonic distortion (thd) 25c iii ?67.2 dbc rxpga gain = 0 db (full-scale = 2.0 v p-p) signal-to-noise and distortion (sinad) full iv 58 59 dbc total harmonic distortion (thd) full iv ?66 ?62.9 dbc rx path composite ac performance @ f adc = 80 msps 3 rxpga gain = 48 db (full-scale = 8.0 mv p-p) signal-to-noise (snr) 25c iii 41.8 dbc total harmonic distortion (thd) 25c iii ?67 dbc rxpga gain = 24 db (full-scale = 126 mv p-p) signal-to-noise (snr) 25c iii 58.6 dbc total harmonic distortion (thd) 25c iii ?62.9 dbc rxpga gain = 0 db (full-scale = 2.0 v p-p) signal-to-noise (snr) 25c ii 58.9 59.6 dbc total harmonic distortion (thd) 25c ii ?69.7 ?59.8 dbc rx-to-tx path full-duplex isolation (1 v p-p, 10 mhz sine wave tx output) rxpga gain = 40 db ioutp pins to rx pins 25c iii 83 dbc ioutg pins to rx pins 25c iii 37 dbc rxpga gain = 0 db ioutp pins to rx pins 25c iii 123 dbc ioutg pins to rx pins 25c iii 77 dbc 1 includes rxpga, adc pipeline, and adio bus delay relative to f adc . 2 f in = 5 mhz, ain = ?1.0 dbfs , lpf cutoff frequency set to 15.5 mhz with reg. 0x08 = 0x80. 3 f in = 5 mhz, ain = ?1.0 dbfs , lpf cutoff frequency set to 26 mhz with reg. 0x08 = 0x80. power supply specifications avdd = 3.3 v, dvdd = clkvdd = drvdd = 3.3 v; r set = 2 k?, full-duplex operation with f data = 80 msps, 1 unless otherwise noted. table 3. parameter temp test level min typ max unit supply voltages avdd full v 3.135 3.3 3.465 v clkvdd full v 3.0 3.3 3.6 v dvdd full v 3.0 3.3 3.6 v drvdd full v 3.0 3.3 3.6 v is_total (total supply current) full ii 406 475 ma power consumption i avdd + i clkvdd (analog supply current) iv 311 342 ma i dvdd + i drvdd (digital supply current) full iv 95 133 ma
AD9865 rev. a | page 6 of 48 parameter temp test level min typ max unit power consumption (half-du plex operation with f data = 50 msps) 2 tx mode i avdd + i clkvdd 25c iv 112 130 ma i dvdd + i drvdd 25c iv 46 49.5 ma rx mode i avdd + i clkvdd 25c iv 225 253 ma i dvdd + i drvdd 25c iv 36.5 39 ma power consumption of functional blocks 1 (i avdd + i clkvdd ) rxpga and lpf 25c iii 87 ma adc 25c iii 108 ma txdac 25c iii 38 ma iamp (programmable) 25c iii 10 120 ma reference 25c iii 170 ma clk pll and synthesizer 25c iii 107 ma maximum allowable power dissipation full iv 1.66 w standby power consumption is_total (total supply current) full 13 ma power down delay (using pwr_dwn pin) rxpga and lpf 25c iii 440 ns adc 25c iii 12 ns txdac 25c iii 20 ns iamp 25c iii 20 ns clk pll and synthesizer 25c iii 27 ns power up delay (using pwr_dwn pin) rxpga and lpf 25c iii 7.8 s adc 25c iii 88 ns txdac 25c iii 13 s iamp 25c iii 20 ns clk pll and synthesizer 25c iii 20 s 1 default power-up settings for mode = high and config = low, ioutp_fs = 20 ma, does not include iamps current consumption, whi ch is application dependent. 2 default power-up settings for mode = low and config = low. digital specifications avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%; r set = 2 k?, unless otherwise noted. table 4. parameter temp test level min typ max unit cmos logic inputs high level input voltage full vi drvdd C 0.7 v low level input voltage full vi 0.4 v input leakage current 12 a input capacitance full vi 3 pf cmos logic outputs (c load = 5 pf) high level output voltage (i oh = 1 ma) full vi drvdd C 0.7 v low level output voltage (i oh = 1 ma) full vi 0.4 v output rise/fall time (high strength mode and c load = 15 pf) full vi 1.5/2.3 ns output rise/fall time (low strength mode and c load = 15 pf) full vi 1.9/2.7 ns output rise/fall time (high strength mode and c load = 5 pf) full vi 0.7/0.7 ns output rise/fall time (low strength mode and c load = 5 pf) full vi 1.0/1.0 ns reset minimum low pulse width (relative to f adc ) 1 clock cycles
AD9865 rev. a | page 7 of 48 serial port timing specifications avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%, unless otherwise noted. table 5. parameter temp test level min typ max unit write operation (see figure 46) sclk clock rate (f sclk ) full iv 32 mhz sclk clock high (t hi ) full iv 14 ns sclk clock low (t low ) full iv 14 ns sdio to sclk setup time (t ds ) full iv 14 ns sclk to sdio hold time (t dh ) full iv 0 ns sen to sclk setup time (t s ) full iv 14 ns sclk to sen hold time (t h ) full iv 0 ns read operation (see figure 47 and figure 48) sclk clock rate (f sclk ) full iv 32 mhz sclk clock high (t hi ) full iv 14 ns sclk clock low (t low ) full iv 14 ns sdio to sclk setup time (t ds ) full iv 14 ns sclk to sdio hold time (t dh ) full iv 0 ns sclk to sdio (or sdo) data valid time (t dv ) full iv 14 ns sen to sdio output valid to hi-z (t ez ) full iv 2 ns half-duplex data interface (adio port) timing specifications avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%, unless otherwise noted. table 6. parameter temp test level min typ max unit read operation 1 (see figure 50) output data rate full ii 5 80 msps three-state output enable time (t pzl ) full ii 3 ns three-state output disable time (t plz ) full ii 3 ns rx data valid time (t vt ) full ii 1.5 ns rx data output delay (t od ) full ii 4 ns write operation (see figure 49) input data rate (1 interpolation) full ii 20 80 msps input data rate (2 interpolation) full ii 10 80 msps input data rate (4 interpolation) full ii 5 50 msps tx data setup time (t ds ) full ii 1 ns tx data hold time (t dh ) full ii 2.5 ns latch enable time (t en ) full ii 3 ns latch disable time (t dis ) full ii 3 ns 1 c load = 5 pf for digital data outputs.
AD9865 rev. a | page 8 of 48 full-duplex data interface (tx and rx port) timing specifications avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%, unless otherwise noted. table 7. parameter temp test level min typ max unit tx path interface (see figure 53) input nibble rate (2 interpolation) full ii 20 160 msps input nibble rate (4 interpolation) full ii 10 100 msps tx data setup time (t ds ) full ii 2.5 ns tx data hold time (t dh ) full ii 1.5 ns rx path interface 1 (see figure 54) output nibble rate full ii 10 160 msps rx data valid time (t dv ) full ii 3 ns rx data hold time (t dh ) full ii 0 ns 1 c load =5 pf for digital data outputs. explanation of test levels i 100% production tested. ii 100% production tested at 25c and guaranteed by de sign and characterization at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c and guaranteed by design and characterization for industrial temperature range.
AD9865 r e v. a | pa ge 9 o f 4 8 absolute maximum ra tings table 8. p a r a me t e r r a t i n g elec tri c a l a v dd , clk v dd v o ltage 3.9 v maximum dvdd , dr vdd v o ltage 3.9 v maximum r x +, rx?, reft , refb ?0.3 v t o a v d d + 0.3 v ioutp+, ioutp? ?1.5 v to a v d d + 0.3 v ioutn+, ioutn?, iout g+, iout g? ?0.3 v to +7 v oscin, x t a l ?0.3 v t o cl vdd + 0.3 v refio , ref a dj ?0.3 v t o a v d d + 0.3 v dig i tal i n put and o utput v o ltag e ?0.3 v t o dr vd d + 0.3 v dig i tal o utput c u rr en t 5 ma max imum environ m en t a l o p era t ing t e mp er a tur e r a nge ( a mbien t ) ?40c to +85c m a ximum junc tion t e mpera tur e 125c l e ad t e mper a tur e (s older i ng , 10 s) 150c stor age t e mpera tur e r a nge ( a mbien t ) ?65c to +150c s t r e s s es a b o v e t h os e list e d u nde r t h e a b s o l u t e m a xim u m r a t i n g s ma y c a us e p e r m an en t da ma g e t o t h e de v i ce . this is a st re ss r a t i n g on l y ; f u nc t i on a l o p e r a t i o n of t h e d e v i c e at t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i ndic a t e d i n t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . thermal c h ar a c teristics ther mal resis t a n ce: 64-lead l f cs p (4-l a y er b o a r d). ja = 24c/w ( p addle s o lder e d t o g r o u n d p l ane , 0 lpm a i r). ja = 30.8c/w (p addle no t s o ld er e d to g r o u nd pla n e, 0 lpm a i r). esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr os ta tic char g e s as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr odu c t f e a tur es pr o p r i etar y esd pr otec tio n cir c u i tr y , per m anen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g es . ther ef o r e , p r ope r esd pr ecaution s ar e r e c o mmended to a v oid per f or m a nc e degrada t ion or l o ss of func tiona l it y .
AD9865 rev. a | page 10 of 48 pin conf igura t ion and fu nction descriptions 4493-0-002 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 49 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 adio9/tx[5] adio8/tx[4] adio7/tx[3] adio6/tx[2] adio5/tx[1] adio4/tx[0] adio3/rx[5] adio2/rx[4] adio1/rx[3] adio0/rx[2] nc/rx[1] nc/rx[0] rxclk t xclk/txquiet txen/txsync rxen/rxsync drv dd d r vss clkout1 sd io sd o sc lk sen gain/pga[ 5 ] pga [ 4] pga [ 3] pga [ 2] pga [ 1] re fb a vss r eset pga [ 0] avss avss iout_n? iout_g? avss avdd refio refadj avdd avss rx+ rx? reft avss avdd avss drv dd d r vss p w r_ dwn clkout2 dv dd d vss clkv dd oscin xta l clkv s s config mo de iout_g+ iout_n+ iout_p ? iout_p+ AD9865 top view (not to scale) pin 1 identifier f i gure 2. pin config ur ation ta ble 9. pi n f u nct i on d e s c ri pt i o ns p i n no . m n emonic mode 1 description 1 adio9 hd msb of adio bu ff er t x [5] fd msb of t x n i bble i n put 2 t o 5 adio8 t o 5 hd bits 8 t o 5 of adi o buff er t x [4 to 1] fd bits 4 to 1 of t x n i bble i n put 6 adio4 hd bit 4 of adio bu ff er t x [0] fd lsb of t x n i bble i n put 7 adio3 hd bit 3 of adio bu ff er rx [5] fd msb of rx n i bbl e o utput 8, 9 adio2, 1 hd bits 2 t o 1 of adi o buff er rx [4, 3] fd bits 4 t o 3 of rx n i bble o utput 10 adio0 hd lsb of adio buf f er rx [2] fd bit 2 of rx n i bble o utput 11 nc hd no c o nnec t rx [1] fd bit 1 of rx n i bble o utput 12 nc hd no c o nnec t rx[0] fd lsb of rx n i bble o utput 13 r x en hd adio buff er c o ntr o l i n put r x sy nc fd rx da ta s y nchr oniza t ion o utput 14 t x en hd t x p a th enable i n put t x sy nc fd t x da ta synchr o n iza t io n i n put
AD9865 rev. a | page 11 of 48 pin no. mnemonic mode 1 description 15 txclk hd adio sample clock input txquiet fd fast txdac/iamp power-down 16 rxclk hd adio request clock input fd rx and tx clock output at 2 x f adc 17, 64 drvdd digital output driver supply input 18, 63 drvss digital output driver supply return 19 clkout1 f adc /n clock output (l = 1, 2, 4, or 8) 20 sdio serial port data input/output 21 sdo serial port data output 22 sclk serial port clock input 23 sen serial port enable input 24 gain fd tx data port (tx[5:0]) mode select pga[5] hd or fd msb of pga input data port 25 to 29 pga[4 to 0] hd or fd bits 4 to 0 of pga input data port 30 reset reset input (active low) 31, 34, 36, 39, 44, 47, 48 avss analog ground 32, 33 refb, reft adc reference decoupling nodes 35, 40, 43 avdd analog power supply input 37, 38 rx?, rx+ receive path ? and + analog inputs 41 refadj txdac full-scale current adjust 42 refio txdac reference input/output 45 iout_g? ?tx amp current output_sink 46 iout_n? ?tx mirror current output_sink 49 iout_g+ +tx amp current output_sink 50 iout_n+ +tx mirror current output_sink 51 iout_p? ?txdac current output_source 52 iout_p+ +txdac current output_source 53 mode digital interface mode select input low = hd, high = fd 54 config power-up spi register default setting input 55 clkvss clock oscillator/synthesizer supply return 56 xtal crystal oscillator inverter output 57 oscin crystal oscillator inverter input 58 clkvdd clock oscillator/synthesizer supply 59 dvss digital supply return 60 dvdd digital supply input 61 clkout2 f oscin /l clock output, (l = 1, 2, or 4) 62 pwr_dwn power-down input 1 hd = half-duplex mode; fd = full-duplex mode.
AD9865 rev. a | page 12 of 48 typical perf orm ance cha r acte ristics rx p a th ty pic a l performance char a c teristics a v dd = c l k v dd = d v dd = dr v d d = 3 . 3 v , f osci n = f ad c = 50 ms ps, lo w-p a s s f i l t er s f ?3 d b = 22 mh z, ain = ?1 db fs, r i n = 5 0 ?, h a lf- o r full - d u p l e x i n t e rfac e , de fa u l t po w e r b i as set t i n g s . 04493- 0- 040 frequency (mhz) input referred spectrum (dbm ) 0 6.25 12.50 18.75 25.00 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 fund = ? 1dbfs sinad = 59.1dbfs enob = 9.53 bits snr = 60.2dbfs thd = ? 65.2dbfs sfdr = ? 64.9dbc (third harmonic) rbw = 12.21khz f i g u re 3. spe c t r al p l ot w i t h 4 k fft of i n put sinus o id with r x pga = 0 db and p in = 9 db m 04493- 0- 041 frequency (mhz) i n put referred spectrum (dbm ) 0 5 10 15 20 25 ?30 ? 130 ? 120 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 rbw = 12.2khz figure 4. spect ra l p l ot w i th 4 k fft of 8 4 -ca rri er dmt s i gn al wit h pa r = 10. 2 db , p in = ?33.7 dbm, and rxpga = 36 db 04493-0-042 input amplitude (dbfs) 0dbfs = 2v p-p sinad (dbfs) thd (dbfs) ?21 ? 18 ? 1 5 ? 12 ?9 ? 6 ?3 0 66 45 48 51 54 57 60 63 ?50 ?92 ?86 ?80 ?74 ?68 ?62 ?56 sinad @ 3.14v sinad @ 3.3v sinad @ 3.46v thd @ 3.14v thd @ 3.3v thd @ 3.46v figure 5. sinad an d thd vs. input amplitude and supply (f in = 8 mh z, lp f f ?3 d b = 26 m h z; rx pg a = 0 db) 04493- 0- 043 rxpga gain (db) si nad (d bf s) en ob (b its ) ?6 0 6 12 18 24 30 36 42 48 62 41 44 47 50 53 56 59 10.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 1mhz 5mhz 10mhz 15mhz 20mhz f i g u re 6. sina d / e n ob v s . r x pga ga in and fr eque ncy 04493- 0- 044 rxpga gain (db) thd (dbfc) ?6 0 6 12 18 24 30 36 42 48 ?5 5 ?8 5 ?8 0 ?7 5 ?7 0 ?6 5 ?6 0 1mhz 5mhz 10mhz 15mhz 20mhz f i g u re 7. t h d v s . r x pga ga in and f r eq uency 04493- 0- 045 rxpga gain (db) s i nad (dbfs ) thd (dbc) ? 6 0 6 12 18 24 30 36 42 48 62 41 44 47 50 53 56 59 ?45 ?80 ?75 ?70 ?65 ?60 ?55 ?50 sinad @ +25 c sinad @ +85 c sinad @ ? 40 c thd @ +25 c thd @ +85 c thd @ ? 40 c f i gure 8. sinad / t h d performan ce vs. rxpga gain and te mper at ur e ( f in = 5 mh z)
AD9865 rev. a | page 13 of 48 0 rx p a th ty pic a l performance char a c teristics a v dd = c l k v dd = d v dd = dr v d d = 3 . 3 v , f osci n = f ad c = 80 ms ps, lo w-p a s s f i l t er s f ?3 d b = 30 mh z, ain = ?1 db fs, r i n = 5 0 ?, h a lf- o r full - d u p l e x i n t e rfac e , de fa u l t po w e r b i as set t i n g s . 04493-0-046 frequency (mhz) inp u t re fe rre d s p e c trum (dbm) 0 1 02 0 3 04 10 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 fund = ? 1dbfs sinad = 59.3dbfs enob = 9.56 bits snr = 59.8dbfs thd = ? 69.1dbfs sfdr = ? 70.3dbc (third harmonic) rbw = 19.53khz f i g u re 9. spe c t r al p l ot w i t h 4k fft of i n put sinus o id wit h r x pga = 0 db and p in = 9 db m 04493-0-047 frequency (mhz) in pu t r e fer r e d spec tr u m ( d b m ) 0 1 02 03 04 ?30 ? 130 ? 120 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 rbw = 19.53khz 0 f i g u re 10. spect ra l pl ot wit h 4k ff t of 11 1-ca rr ier dm t si g n al wit h pa r = 11 d b , p in = ? 3 3 . 7 dbm , lp f f ?3 d b = 32 m h z, a n d r x pga = 36 db 04493-0-048 input amplitude (dbfs) 0dbfs = 2v p-p s i nad (dbfs ) thd (dbfs ) ? 2 1 ? 18 ?15 ? 12 ?9 ?6 ?3 0 66 45 48 51 54 57 60 63 ?50 ?92 ?86 ?80 ?74 ?68 ?62 ?56 sinad @ 3.14v sinad @ 3.3v sinad @ 3.46v thd @ 3.14v thd @ 3.3v thd @ 3.46v f i gure 11. sinad and thd vs. input a m plitude and s u pp ly (f in = 8 mh z, lp f f ?3 d b = 26 m h z; r x pga = 0 db) 04493-0-049 rxpga gain (db) s i nad (dbfs ) enob ( b it s) ?6 0 6 12 18 24 30 36 42 48 62 41 44 47 50 53 56 59 10.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 5mhz 10mhz 15mhz 20mhz 30mhz f i gure 12. sinad/e n ob vs. rxpga gain and frequ e ncy 04493-0-050 rxpga gain (db) thd (dbc ) ? 6 0 6 12 18 24 30 36 42 48 ? 55 ?8 5 ?8 0 ?7 5 ?7 0 ?6 5 ?6 0 5mhz 10mhz 15mhz 20mhz 30mhz f i g u re 13. th d v s . r x pga gai n a n d fr equen c y 04493-0-051 rxpga gain (db) s i nad (dbfs ) thd (dbc ) ? 6 0 6 12 18 24 30 36 42 48 62 41 44 47 50 53 56 59 ? 40 ?75 ?70 ?65 ?60 ?55 ?50 ?45 sinad @ +25 c sinad @ +85 c sinad @ ? 40 c thd @ +25 c thd @ +85 c thd @ ? 40 c f i g u re 14. sina d/ t h d pe rf or m a nc e v s . r x pga ga in and t e mp er at ure ( f in = 1 0 m h z)
AD9865 rev. a | page 14 of 48 04493-0-052 input frequency (mhz) s nr (dbfs ) thd (dbc ) ?6 0 6 12 18 24 30 36 42 48 61.0 60.5 60.0 59.5 59.0 58.5 58.0 57.5 57.0 56.5 56.0 ? 52 ?54 ?56 ?58 ?60 ?62 ?64 ?66 ?68 ?70 ?72 snr @ 3.13v snr @ 3.3v snr @ 3.47v thd @ 3.13v thd @ 3.3v thd @ 3.47v f i gure 15. snr and thd vs. input f r eq uency and supp ly ( lpf f ?3 d b = 2 6 mh z; rxpga = 0 d b ) 04493-0-053 rxpga gain (db) in tegr a t ed n o ise ( v rms) n o ise spec tr a l d e n s ity ( n v/ h z ) ?6 0 6 12 18 24 30 36 42 48 109.4 98.5 87.5 76.6 65.6 54.7 43.8 32.8 21.9 10.9 0 20 18 16 14 12 10 8 6 4 2 0 AD9865: +25 c AD9865: +85 c AD9865: ?40 c f i gure 16. input r e f e rr ed integr ated n o ise and no ise sp e c tra l d e nsity v s . r x pga gai n (lpf f ?3 db = 26 mh z) 04493-0-054 gain (db) d c offset ( % of f u ll- scale) ? 6 0 6 12 18 24 30 36 42 48 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 device 1 device 2 device 3 device 4 f i gur e 1 7 . rx dc of fse t vs. rxp g a ga i n 04493-0-055 input frequency (mhz) s nr (dbfs ) thd (dbc ) 20 30 40 50 60 70 80 60.0 55.0 ?20 ?70 ?60 ?50 ?40 ?30 55.5 56.0 56.5 57.0 57.5 58.0 58.5 59.0 59.5 snr @ 3.13v snr @ 3.3v snr @ 3.46v thd @ 3.13v thd @ 3.3v thd @ 3.46v f i gure 18. snr and thd vs. s a mple rate and supply (lpf dis a bled; rxpga = 0 db; f in = 8 m h z) 04493-0-056 cutoff frequency (mhz) s nr (dbc ) 0 1 02 0 3 04 0 5 06 07 0 8 0 45 44 43 42 41 40 39 38 f i g u re 19. snr v s . f ilt e r cut o f f fr eque n c y (50 m s ps; f in = 5 m h z; ain = ? 1 db; rxpga = 48 db) 04493-0-057 rxpga gain (db) gain s t e p e rror (db) ?6 0 6 12 18 24 30 36 42 48 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 AD9865: gain step error @ +25 c AD9865: gain step error @ +85 c AD9865: gain step error @ ? 40 c f i gure 20. r x pga g a in step e r ro r v s . g a in (f in = 10 mh z)
AD9865 rev. a | page 15 of 48 rx p a th ty pic a l performance char a c teristics a v dd = c l k v dd = d v dd = dr v d d = 3 . 3 v , f osci n = f ad c = 50 ms ps, lo w-p a s s f i l t er dis a b l e d , rxpg a = 0 db , ai n = ?1 db fs, r i n = 5 0 ?, h a lf- o r full - d u p l e x i n t e rfac e , de fa u l t po w e r b i as set t i n g s . 04493-0-058 time (ns) code 0 8 0 160 240 320 400 480 560 640 720 512 64 128 192 256 320 384 448 f i g u re 21. r x pga s e t t ling t i me ?1 2 d b t o +4 8 db tr ans i t i on f o r dc input (f ad c = 50 msps, lp f disab l ed) 04493-0-059 input frequency (mhz) a m plitu d e r espon se ( d b ) 0 5 10 15 20 25 30 35 40 45 50 0 ?18 ?15 ?12 ?9 ?6 ?3 3.3v 3.0v 3.6v f i gur e 2 2 . rx lo w- p a ss fil t er am p l i t ude respo n se vs. suppl y (f ad c = 50 msps , f ?3 d b = 33 m h z, r x pga = 0 db) 04493-0-060 frequency (mhz) atten @rxp g a = 0d b (db) 0 5 10 15 20 25 30 35 140 60 70 80 90 100 110 120 130 txdac isolation @ 0db iamp isolation @ 0db f i g u re 23. r x t o tx full-dup l ex is ol at i o n @ 0 r x pga s e t t i ng (note: atten @ r x pg a = x db = atten @ r x pga = 0 db ? r x pga g a i n ) 04493-0-061 time (ns) code 0 8 0 160 240 320 400 480 560 640 720 352 320 288 256 224 192 160 128 96 64 f i gure 24. rxpga s e ttling t i me f o r 0 d b to +5 d b tr ansit i on fo r dc input (f ad c = 50 msps, lp f disab l ed) 04493-0-062 input frequency (mhz) fundame n tal (db) 0 5 10 15 20 25 30 35 40 50 45 0 ?20 ?16 ?18 ?14 ?12 ?10 ?8 ?6 ?2 ?4 ?6db gain 0db gain +6db gain +18db gain +30db gain +42db gain f i gur e 2 5 . rx lo w- p a ss fil t er am p l i t ude respo n se vs. rxp g a gai n (lpf's f ? 3 db = 33 m h z) 04493-0-090 frequency (mhz) re s i s t ance ( ? ) cap acitance (pf) 5 105 95 85 75 65 55 45 35 25 15 420 320 10 0 1 2 3 4 5 6 7 8 9 330 340 350 360 370 380 390 400 410 r in c in f i gure 26. rx input imped a nc e vs. fr eq uency
AD9865 rev. a | page 16 of 48 txd a c p a th ty pic a l pe rformanc e char a c teristics a v dd = c l k v dd = d v dd = dr v d d = 3 . 3 v , f osci n = 50 m s ps a nd 80 ms ps, rs et = 1.96 k?, 2:1 tra n sf o r m e r co u p led ou t p u t (s ee f i gur e 63) in t o 50 ? lo ad half- o r f u l l -d u p l e x in t e r f ac e , def a u l t p o w e r b i as s e t t in gs. 04493-0-072 frequency (mhz) dbm 0 5 10 15 20 30 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 f i g u re 27. d u al- t o n e spe c t r a l plot of t x da c's o u t p ut (f da t a = 5 0 m s ps, 4 int e rpol at i o n, 10 dbm p e ak p o wer , f1 = 1 7 m h z, f 2 = 18 m h z) 04493-0-073 2-tone center frequency (mhz) imd (dbfs ) (r ela t i ve to pea k power ) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 28. 2- t o ne i m d f r equenc y s w e e p vs. p e ak p o wer with f da t a = 50 msps, 4 inte r p o l a t io n 04493-0-074 2-tone center frequency (mhz) s f dr (dbfs ) (r ela t i ve to pea k power ) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 29. 2- t o ne w o rs t spur f r equ e nc y s w eep v s . p e ak p o w e r with f da t a = 50 msps, 4 inte r p o l a t io n 04493-0-075 frequency (mhz) dbm 0 5 10 15 20 25 30 35 40 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 f i g u re 30. d u al- t o n e spe c t r a l plot of t x da c's o u t p ut (f da t a = 8 0 m s ps, 2 int e rpol at i o n, 10 dbm p e ak p o wer , f1 = 2 7 .1 mh z, f 2 = 2 8 . 7 mh z) 04493-0-076 2-tone center frequency (mhz) imd (dbfs ) (r ela t i ve to pea k power ) 0 5 10 15 20 25 30 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 31. 2- t o ne i m d f r equenc y s w e e p vs. p e ak p o wer with f da t a = 80 msps, 2 inte r p o l a t io n 04493-0-077 2-tone center frequency (mhz) s f dr (dbfs ) (r ela t i ve to pea k power ) 0 5 10 15 20 25 30 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 32. 2- t o ne w o rs t spur f r equ e nc y s w eep v s . p e ak p o w e r with f da t a = 80 msps, 2 inte r p o l a t io n
AD9865 rev. a | page 17 of 48 04493-0-078 frequency (mhz) dbm 0 5 10 15 20 25 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 par = 11.4 rms = ? 1.4dbm f i g u re 33. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r (f da t a = 5 0 m s ps, 4 int e rpol at i o n) 04493-0-079 frequency (mhz) dbm 0 2 5 5 0 7 5 100 125 150 175 200 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 par = 11.4 rms = ? 1.4dbm f i g u re 34. wideb a n d spec t r al pl ot of 8 8 -subc a r r ie r ofdm t e s t v e c t or (f da t a = 5 0 m s ps, 4 int e rpol at i o n) 04493-0-080 aout (dbfs) s nr and 2 - tone imd (dbfs ) (r ela t i ve to pea k power ) ?2 4 ? 2 1 ?1 8 ? 1 5 ?1 2 ? 9 ? 6 ? 3 0 100 55 60 65 70 75 80 85 90 95 2-tone imd snr f i gure 35. snr and sfdr vs. p ou t (f ou t = 1 2 .5 5 m h z, f da t a = 5 0 m s ps, 4 i n terpol at i o n) 04493-0-081 frequency (mhz) dbm 0 5 10 15 20 25 30 35 40 ?20 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 par = 11.4 rms = ? 1.4dbm f i g u re 36. spec t r a l p l ot of 1 11- ca rr ie r ofdm t e s t v e c t o r (f da t a = 8 0 m s ps, 2 int e rpol at i o n) 04493-0-082 frequency (mhz) dbm 0 2 0 4 0 6 0 8 0 100 120 140 160 ?20 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 par = 11.4 rms = ? 1.4dbm f i g u re 37. wideb a n d spec t r al pl ot of 1 11- ca rri er ofdm t e s t v e c t o r (f da t a = 8 0 m s ps, 2 int e rpol at i o n) 04493-0-083 aout (dbfs) s nr and 2 - tone imd (dbfs ) (r ela t i ve to pea k power ) ?2 4 ? 2 1 ?1 8 ? 1 5 ?1 2 ? 9 ? 6 ? 3 0 95 55 60 65 70 75 80 85 90 snr 2-tone imd f i gure 38. snr and sfdr vs. p ou t (f ou t = 2 0 mh z, f da t a = 80 m s ps, 2 int e rpo l at i o n)
AD9865 rev. a | page 18 of 48 iamp p a th ty pic a l pe rformanc e char a c teristics a v dd = c l k v dd = d v dd = dr v d d = 3 . 3 v , f osci n = 50 m s ps, r set = 1.58 k?, 1:1 tra n sf o r m e r co u p le d o u t p u t (s ee f i gur e 64 a nd f i gur e 65) in t o 50 ? lo ad , half- o r f u l l -d u p lex in t e r f ac e , def a u l t p o w e r b i as s e t t in gs. 04493- 0- 084 frequency (mhz) dbm 0 5 10 15 20 25 20 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 rbw = 2.3khz f i g u re 39. d u al- t o n e spe c t r a l plot of i a m p n o u t p ut (ia m p s e tti ngs of i = 1 2 . 5 ma, n = 4, g = 0, 2:1 t r ans f o r m e r int o 7 5 ? l o ade r , v c m = 4.8 v ) 04493- 0- 085 frequency (mhz) dbm 0 5 10 15 20 25 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 par = 11.4 rms = 10.3dbm f i g u re 40. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r u s ing ia m p n in c u rrent-mode c o nfigur ation (ia m p s e t t i ng s of i = 1 0 ma, n = 4, g = 0; v c m = 4. 8 v ) 04493- 0- 086 frequency (mhz) dbm 0 5 10 15 20 25 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 par = 11.4 rms = 10.4dbm f i g u re 41. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r u s ing ia m p in v o lt ag e - m o d e con f ig ur at i o n wit h a v dd = 5 v (pbr 9 51 t r ans i s t or s, ia m p s e t t i ng s of i = 6 ma, n = 2, g = 6) 04493- 0- 087 vcm (v) oip3 ( d bm) 3.0 3.5 4.0 4.5 5.0 48 5mhz 10mhz 15mhz 20mhz 2.5mhz 30 46 44 42 40 38 36 34 32 f i g u re 42. iou t n t h ir d- o r d e r i n te r c ep t v s . com m on-m od e v o lt ag e (ia m p s e tti ngs of i = 1 2 . 5 ma, n = 4, g = 0, 2:1 t r a n s f or me r i n to 7 5 ? l oad) 04493- 0- 088 vcm (v) oip3 (dbm) 3.0 3.5 4.0 4.5 5.0 42 5mhz 10mhz 15mhz 20mhz 2.5mhz 30 40 38 36 34 32 f i g u re 43. iou t g t h ir d- o r d e r i n te r c ep t v s . com m on-m od e v o lt ag e (ia m p s e tti ngs of i = 4. 2 5 ma, n = 0, g = 6, 2 : 1 t r a n sfor me r i n to 75 ? l o a d ) 04493- 0- 089 frequency (mhz) dbm 0 5 10 15 20 25 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 par = 11.4 rms = 9.8dbm rbw = 10khz f i g u re 44. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r u s ing ia m p in v o lt ag e - m o d e con f ig ur at i o n wit h a v dd = 3. 3 v (pbr 9 51 t r ans i s t or s, ia m p s e t t i ng s of i = 6 ma, n = 2, g = 6)
AD9865 rev. a | page 19 of 48 serial port table 10. spi register mapping power-up default value mode = 0 (half-duplex) mode = 1 (full-duplex) address (hex) 1 bit break- down description width config = 0 config = 1 config = 0 config = 1 comments spi port configuration and software reset 0x00 (7) 4-wire spi 1 0 0 0 0 (6) lsb first 1 0 0 0 0 (5) s/w reset 1 0 0 0 0 default spi configuration is 3-wire, msb first. power control registers (via pwr_dwn pin) 0x01 (7) clock syn. 1 0 0 0 0 (6) txdac/iamp 1 0 0 0 0 (5) tx digital 1 0 0 0 0 (4) ref 1 0 0 0 0 (3) adc cml 1 0 0 0 0 (2) adc 1 0 0 0 0 (1) pga bias 1 0 0 0 0 (0) rxpga 1 0 0 0 0 pwr_dwn = 0. default setting is for all blocks powered on. 0x02 (7) clk syn. 1 0 0 0 1* (6) txdac/iamp 1 1 1 1 1 (5) tx digital 1 1 1 1 1 (4) ref 1 1 1 1 1 (3) adc cml 1 1 1 1 1 (2) adc 1 1 1 1 1 (1) pga bias 1 1 1 1 1 (0) rxpga 1 1 1 1 1 pwr_dwn = 1. default setting* is for all functional blocks powered down except pll. *mode = config = 1. setting has pll powered down with oscin input routed to rxclk output. half-duplex power control 0x03 (7:3) tx off delay 5 (2) rx _txen 1 (1) tx pwrdn 1 (0) rx pwrdn 1 0xff 0xff n/a n/a default setting is for txen input to control power on/off of tx/rx path. tx driver delayed by 31 1/f data clock cycles. pll clock multiplier/synthesizer control 0x04 (5) duty cycle enable 1 0 0 0 0 (4) f adc from pll 1 0 0 0 0 (3:2) pll divide-n 2 00 00 00 00 (1:0) pll multiplier-m 2 01 10* 01 01 default setting is duty cycle restore disabled, adc clk from oscin input, and pll multiplier 2 setting. *pll multiplier 4 setting. 0x05 (2) oscin to rxclk 1 0 0 0 1* (1) invert rxclk 1 0 0 0 0 (0) disabled rxclk 1 0 0 0 0 full-duplex rxclk normally at nibble rate. *exception on power-up. 0x06 (7:6) clkout2 divide 2 01 01 01 01 (5) clkout2 invert 1 0 0 0 0 (4) clkout2 disable 1 0 0 0 1* (3:2) clkout1 divide 2 01 01 01 01 (1) clkout1 invert 1 0 0 0 0 (0) clkout1 disable 1 0 0 0 1* default setting is clkout2 and clkout1 enabled with divide-by-2. *clkout1 and clkout2 disabled. rx path control 0x07 (5) initiate offset cal. 1 0 0 0 0 (4) rx low power 1 0 1* 0 1* (0) rx filter on 1 1 1 1 1 default setting has lpf on and rx path at nominal power bias setting. *rx path to low power.
AD9865 rev. a | page 20 of 48 power-up default value mode = 0 (half-duplex) mode = 1 (full-duplex) address (hex) 1 bit break- down description width config = 0 config = 1 config = 0 config = 1 comments 0x08 (7:0) rx filter tuning cut-off frequency 8 0x80 0x61 0x80 0x80 refer to low-pass filter section. tx/rx path gain control 0x09 (6) use spi rx gain 1 (5:0) rx gain code 6 0x00 0x00 0x00 0x00 default setting is for hardware rx gain code via pga or tx data port. 0x0a (6) use spi tx gain 1 (5:0) tx gain code 6 0x7f 0x7f 0x7f 0x7f default setting is for tx gain code via spi control. tx and rx pga control 0x0b (6) pga code for tx 1 0 0 0 0 (5) pga code for rx 1 1 1 1 1 (3) force gain strobe 1 0 0 0 0 (2) rx gain on tx port 1 0 0 1* 1* (1) 3-bit rxpga port 1 0 1** 0 0 default setting is rxpga control active. *tx port with gain strobe (ad9875/ad9876-compatible). ** 3-bit rxpga gain map (ad9975-compatible). tx digital filter and interface 0x0c (7:6) interpolation factor 2 01 00 01 01 (4) invert txen/txsync 1 0 0 0 0 (3) tx 5/5 nibble* 1 n/a n/a 0 0 (2) ls nibble first* 1 n/a n/a 0 0 (1) txclk neg. edge 1 0 0 0 0 (0) twos complement 1 0 0 1 1 default setting is 2 interpolation with lpf response. data format is straight binary for half- duplex and twos complement for full-duplex interface. *full-duplex only. rx interface and analog/digital loopback 0x0d (7) analog loopback 1 0 0 0 0 (6) digital loopback* 1 0 0 0 0 (5) rx port 3-state 1 n/a n/a 0 0 (4) invert rxen/rxsync 1 0 0 0 0 (3) rx 5/5 nibble 1 n/a n/a 0 0 (2) ls nibble first* 1 n/a n/a 0 0 (1) rxclk neg. edge 1 0 0 0 0 (0) twos complement 1 0 0 1 1 data format is straight binary for half-duplex and twos complement for full- duplex interface. analog loopback: adc rx data fed back to txdac. digital loopback: tx input data to rx output port. *full-duplex only. digital output drive strength, txdac output, and rev id 0x0e (7) low drive strength 1 0 0 0 0 (0) txdac output 1 0 0 0 0 0x0f (3:0) rev id number 4 0x00 0x00 0x00 0x00 default setting is for high drive strength and iamp enabled. tx iamp gain and bias control 0x10 (7) select tx gain 1 (6:4) g1 3 (2:0) n 3 0x44 0x44 0x44 0x44 secondary path g1 = 0, 1, 2, 3, 4. primary path n = 0, 1, 2, 3, 4. 0x11 (6:4) g2 3 (2:0) g3 3 0x62 0x62 0x62 0x62 secondary path stages: g2 = 0 to 1.50 in 0.25 steps and g3 = 0 to 6. 0x12 (6:4) stand_secondary 3 (2:0) stand_primary 3 0x01 0x01 0x01 0x01 standing current of primary and secondary path.
AD9865 rev. a | page 21 of 48 power-up default value mode = 0 (half-duplex) mode = 1 (full-duplex) address (hex) 1 bit break- down description width config = 0 config = 1 config = 0 config = 1 comments (7:5) cpga bias adjust 3 (4:3) spga bias adjust 2 0x13 (2:0) adc bias adjust 4 0x00 0x00 0x00 0x00 current bias setting for rx paths functional blocks. refer to page 41. 1 bits that are undefined should always be assigned a 0. register map description the AD9865 contains a set of programmable registers described in table 10 that are used to optimize its numerous features, interface options, and performance parameters from its default register settings. registers pertaining to similar functions have been grouped together and assigned adjacent addresses to minimize the update time when using the multibyte serial port interface (spi) read/write feature. bits that are undefined within a register should be assigned a 0 when writing to that register. the default register settings were intended to allow some applications to operate without the use of an spi. the AD9865 can be configured to support a half- or full-duplex digital interface via the mode pin, with each interface having two possible default register settings determined by the setting of the config pin. for instance, applications that need to use only the tx or rx path functionality of the AD9865 can configure it for a half- duplex interface (mode = 0), and use the txen pin to select between the tx or rx signal path with the unused path remaining in a reduced power state. the config pin can be used to select the default interpolation ratio of the tx path and rxpga gain mapping. serial port interface (spi) the serial port of the AD9865 has 3- or 4-wire spi capability allowing read/write access to all registers that configure the devices internal parameters. registers pertaining to the spi are listed in table 11. the default 3-wire serial communication port consists of a clock (sclk), serial port enable ( sen ), and a bi- directional data (sdio) signal. sen is an active low control gating read and write cycle. when sen is high, sdo and sdio are three-stated. the inputs to sclk, sen , and sdio contain a schmitt trigger with a nominal hysteresis of 0.4 v centered about vddh/2. the sdo pin remains three-stated in a 3-wire spi interface. table 11. spi registers pertaining to spi options address (hex) bit description 0x00 (7) enable 4-wire spi (6) enable spi lsb first a 4-wire spi can be enabled by setting the 4-wire spi bit high , causing the output data to appear on the sdo pin instead of on the sdio pin. the sdio pin serves as an input-only throughout the read operation. note that the sdo pin is active only during the transmission of data and remains three-stated at any other time. an 8-bit instruction header must accompany each read and write operation. the instruction header is shown in table 12. the msb is an r/ w indicator bit with logic high indicating a read operation. the next two bits, n1 and n0, specify the number of bytes (one to four bytes) to be transferred during the data transfer cycle. the remaining five bits specify the address bits to be accessed during the data transfer portion. the data bits immediately follow the instruction header for both read and write operations. table 12. instruction header information msb lsb 17 16 15 14 13 12 11 10 r/ w n1 n0 a4 a3 a2 a1 a0 the AD9865 serial port can support both msb (most significant bit) first and lsb (least significant bit) first data formats. figure 45 illustrates how the serial port words are built for the msb first and lsb first modes. the bit order is con- trolled by the spi lsb first bit (register 0, bit 6). the default value is 0, msb first. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. the AD9865 automatically decrements the address for each succes- sive byte required for the multibyte communication cycle.
AD9865 rev. a | page 22 of 48 sc l k s dat a sc l k s dat a r/ w n1 a1 a2 a3 a4 a0 n2 d7 1 d6 1 d1 n d0 n r/ w n1 a1 a2 a3 a4 a0 n 2 d0 1 d1 1 d7 n d6 n 4493-0-003 dat a t rans f e r c y c l e i n st r u c t i o n c yc l e da t a t rans f e r c y c l e i n s t ruct i o n c y c l e sen sen f i gure 45. spi ti ming , msb f i rst (up p er), and lsb f i rst (l ow er) w h e n th e s p i l s b fi r s t b i t i s s e t h i g h , th e s e ri a l p o rt i n t e rp r e t s b o t h inst r u c t io n an d d a t a b y t e s ls b f i rst. m u l t ib y t e da t a t r a n s - fers in ls b fo r m a t can b e com p let e d b y wr i t ing a n inst r u c t io n b y t e t h a t i n cl udes t h e reg i s t er addr es s o f t h e f i rs t ad dr ess t o b e acces s e d . the AD9865 a u t o ma tical l y in cr em en ts th e addr es s f o r e a ch succe s si v e b y t e r e q u ir e d fo r t h e m u l t ib y t e co mm un ic a t io n cy c l e . f i gur e 46 i l l u s t ra t e s t h e t i min g r e q u ir emen t s fo r a wr i t e o p er a - tio n t o t h e s p i p o r t . af t e r th e s e r i al p o r t enab l e ( se n ) signal g o es lo w , da ta ( s d i o) p e r t a i nin g t o t h e in s t r u c t io n h e ader is r e ad o n t h e r i si n g e d ges o f t h e clo c k (sclk). t o ini t ia t e a wr i t e o p era t ion, t h e re ad/ n ot- w r i t e b i t is s e t lo w . af t e r t h e i n st r u c t ion h e ader is r e ad , t h e eig h t da t a b i ts p e r t a i nin g t o t h e sp ecif ie d r e g i s t er a r e s h if ted in t o t h e s d i o p i n on t h e r i sin g edge o f the nex t e i g h t cl o c k c y cl es . i f a m u l t ib y t e c o m m u n i c a t ion c y cl e is sp e c if ie d , t h e de st ina t io n a ddr ess is de cr em e n te d (ms b f i rst) and sh if ts i n anot h e r e i g h t b i t s of d a t a . thi s p r o c e s s re p e a t s u n t i l a l l t h e b y t e s sp e c if ie d i n t h e in st r u c t io n h e a d er (n1, n0 b i t s ) a r e sh i f te d i n to t h e sdio pi n . se n m u s t r e ma in lo w d u r i ng t h e d a t a t r a n sfer o p era t io n, o n ly go in g hig h a f t e r t h e la st b i t is shif t e d in t o t h e s d i o pin. d7 d6 a0 d1 se n n1 n0 t s scl k sd i o 1/ f sclk t low t hi t ds t dh r/w d0 t h 4493- 0- 004 f i g u re 46. spi w r it e o p er at io n ti ming f i g u re 4 7 i l lu st r a te s t h e t i m i ng f o r a 3 - w i re re a d op e r a t i o n to th e s p i po r t . a f t e r se n g o es lo w , da ta (s d i o) p e r t aining t o t h e in st r u c t io n h e a d er is r e ad o n t h e r i sin g e d ges o f sclk. a r e a d o p era t ion o c c u rs, if t h e r e ad / n ot- w r i t e i n d i c a t o r is s e t hig h . af t e r t h e addr ess b i ts o f t h e ins t r u c t io n h e ader a r e r e ad , t h e eig h t da t a b i ts p e r t a i nin g to t h e sp e c if ie d r e g i ste r a r e shif te d o u t o f th e s d i o p i n o n th e f a lli n g ed g e s o f th e n e xt e i gh t c l oc k c y c l e s . i f a m u l t ib y t e com m u n i c a t ion c y cle is sp e c if ie d i n t h e inst r u c t ion h e ad er , a sim i lar p r o c ess as p r e v io usly des c r i b e d fo r a m u l t ib y t e s p i wr i t e op era t io n a p pl ies. th e s d o p i n r e ma i n s t h r e e- s t a t e d i n a 3 - w i re re a d op e r a t i o n . d7 d6 a0 d1 sen n1 t s s cl k sd i o 1/ f sclk t low t hi t ds t dh r/w d0 t ez a2 a1 t dv 4493- 0- 005 f i g u re 47. spi 3-w i re r e ad o p er at i o n tim i ng f i g u re 4 8 i l lu st r a te s t h e t i m i ng f o r a 4 - w i re re a d op e r a t i o n to t h e s p i p o r t . the t i min g is simi l a r t o t h e 3 - w i r e r e ad o p era t io n wi t h t h e excep t io n t h a t da t a a p p e a r s a t t h e sd o p i n, w h ile t h e s d i o p i n r e mai n s hig h i m p e dan c e t h r o ug h o u t t h e op er a t ion. t h e s d o p i n i s a n a c ti v e o u t p u t o n l y d u ri n g t h e da ta tra n sf e r phas e an d r e main s t h r e e - st a t e d a t a l l o t h e r t i m e s. a0 se n n1 t s scl k sd i o 1/ f sclk t low t hi t ds t dh r/w t ez a2 a1 t dv d7 d6 d1 sdo d0 t ez 4493- 0- 006 f i g u re 48. spi 4-w i re r e ad o p er at i o n tim i ng
AD9865 rev. a | page 23 of 48 digit a l i n terf ace the dig i t a l in t e r f ace p o r t is co nf igura b le f o r half-d u p lex o r f u l l - d u plex o p er a t io n b y pin- st r a p p i n g t h e mode p i n lo w o r hig h , r e s p e c ti ve l y . i n half-d u p lex m o de , t h e dig i tal in t e r f ace p o r t be com e s a 10 -b i t b i dir e c t io nal b u s cal l e d t h e a d i o p o r t . i n f u l l -d u p lex mo de, t h e dig i t a l in ter f ace p o r t is d i vi de d in to tw o 6-b i t po r t s calle d t x [5:0] a n d rx[5:0] f o r si m u l t a n eo us t x a n d rx o p era t io n s . i n t h is m o de , d a t a is t r a n sfer r e d b e tw e e n t h e as i c a nd ad9 865 in 6-b i t (o r 5-b i t) ni b b l es . th e AD9865 als o fe a t ur es a f l exi b le dig i t a l in ter f ace fo r u p da t i n g t h e rxpga and txpga ga i n r e g i st ers v i a a 6- b i t pga p o r t o r t x [ 5 :0] p o r t fo r fas t u p da t e s, o r v i a t h e s p i p o r t fo r s l o w er u p da t e s. s e e t h e rxpga c o n t r o l s e c t io n fo r m o re info r m a t io n. half-dupl e x mode the half-d u p lex m o de f u n c tio n s as f o l l o w s wh e n t h e m o d e p i n is t i e d lo w . the b i dir e c t io n a l adi o p o r t is ty p i c a l l y sha r e d in b u rst fa shion b e tw e e n t h e t r an smi t p a t h and r e cei v e p a t h . t w o con t r o l sig n als, t x e n an d r x e n , f r o m a ds p (o r dig i tal a s ic ) c o n t ro l t h e bu s d i re c t i o n b y e n abl i ng t h e a d io p o r t s in p u t l a tch an d o u t p ut dr i v er , resp e c t i vely . t w o clo c k sig n a l s a r e a l s o u s e d : t x c l k to l a tc h t h e tx i n put d a t a , a nd r x c l k to clo c k t h e rx o u tp u t da t a . the a d i o p o r t ca n a l s o b e dis a b l e d b y s e t t in g t x e n an d r x e n lo w (defa u l t s e t t ing), th us al lo wing i t to b e c o n n e c t e d to a sh are d bu s . i n ter n a l ly , t h e ad i o p o r t co nsists o f a n i n p u t la t c h fo r t h e tx pa th in pa ralle l w i th a n o u t p u t la t c h wi t h th r e e - s t a t e o u t p u t s f o r th e rx p a th. t x en is us ed t o ena b le t h e in p u t la t c h; r x e n is us e d t o t h r e e- s t a t e t h e o u t p u t l a t c h. a f i v e -s am ple-de ep fifo i s us e d o n t h e tx a nd rx p a t h s t o a b s o rb an y phas e dif f er en ce b e - tw een t h e ad9 865 s in t e r n al c l o c ks an d the exter n al l y s u p p lied clo c ks (t x c l k , r x c l k). t h e adi o b u s acc e p t s i n p u t d a t a - w o r d s i n t o th e tr a n s m i t pa t h wh e n th e t x en p i n i s h i gh , th e r x e n p i n is lo w , and a clo c k is p r es en t o n t h e t x clk pin, as sh ow n i n fi g u re 4 9 . tx c l k t xen adi o [ 9: 0 ] r xen tx 0 tx 2 tx 3 t x 4 tx 1 t dis 4493-0-007 t dh t en t ds f i gure 4 9 . t r a n s m i t d a ta inp u t t i mi ng di a g r a m the tx i n ter p ola t io n f i l t er(s) fo l l o w i n g t h e ad io p o r t ca n b e f l us h e d wi th z e r o s, i f th e c l ock si gn al in t o t h e t x c l k p i n i s p r es en t fo r 33 clo c k c y cles a f t e r t x e n g o es lo w . n o t e t h a t t h e d a t a on t h e adio b u s is ir r e le van t o v er t h is in t e r v a l . the o u t p u t f r o m t h e r e cei v e p a t h is dr i v e n o n t o t h e ad i o b u s w h en t h e r x en p i n i s hi g h , a n d a cl o c k i s p r es e n t o n t h e r x clk p i n. w h i l e t h e ou t p ut l a tch is e n a b le d b y r x en, va lid d a t a a p p e ars on t h e b u s af te r a 6 - cl o c k - c y cl e de l a y du e to t h e i n te r n a l fifo de l a y . n o te tha t rx da t a is n o t la t c hed back in t o t h e tx p a t h , if t x e n i s hig h d u r i n g t h is in t e r v a l w i t h t x clk p r es e n t . t h e ad i o b u s bec o m e s th r e e - s t a t e d o n c e th e r x en p i n r e t u rn s lo w . f i gur e 50 sh o w s t h e r e cei v e p a th o u t p u t timing. t pzl 4493-0-008 r xen a di o [ 9: 0 ] rx c l k t vt t plz t od rx0 rx1 rx2 rx3 f i gure 50. rec e ive d a t a o u tput tim i n g d i ag r a m t o add f l exi b i l i t y t o t h e dig i t a l i n t e r f ac e p o r t , s e v e ral p r og ra m- min g o p t i o n s a r e a v a i lab l e i n t h e s p i r e g i s t ers. th e s e o p t i o n s a r e lis t e d in t a ble 13. th e de fa u l t tx an d rx da t a in p u t fo r m a t s a r e st r a ig h t b i nar y , b u t can b e cha n ge d to tw o s co m p le m e n t . the def a u l t t x en an d r x e n s e t t in gs a r e ac t i ve hig h , b u t can b e se t t o o p po s i t e po l a ri ti e s , th u s a l l o w i n g th e m t o s h a r e th e s a m e co n t r o l . i n this cas e , t h e ad i o p o r t can s t il l b e p l ace d on to a sh are d bu s b y d i s a bl i n g it s i n put l a tc h v i a t h e c o n t rol sig n al , an d dis a b l in g t h e o u t p u t dr i v er v i a t h e sp i r e g i s t er . the clo c k t i m i n g can b e i n d e p e nde n t ly cha n ge d on t h e t r an smi t a nd r e cei v e p a t h s b y s e le c t in g e i t h er t h e r i si n g o r fal l in g clo c k e d g e a s th e v a lida tin g / s a m p l i n g e d g e o f th e c l ock . l a s t l y , t h e o u t p u t dr i v er s st r e n g t h ca n b e r e d u ce d fo r lo w e r da t a r a te a p plic a t io ns. table 13. spi r e gisters for half-du p lex i n terface a ddress (he x ) b i t d e s c r i p t i o n 0x0c ( 4 ) i n v e r t t x e n (1) t x clk nega tiv e edge ( 0 ) t w os complemen t 0x0d (5) rx por t thr e e - s t a t e (4) i n v e r t r x en (1) r x clk nega tiv e edge ( 0 ) t w os complemen t 0x0e (7) l o w dig i tal driv e s t r e ngth the ha lf- d u p lex in t e r f a c e can b e co nf igur e d t o ac t as a sl a v e o r a mas t er t o t h e dig i t a l as i c . a n e x a m ple o f a sla v e co nf igura t io n is s h o w n in f i g u r e 51. i n this exa m p l e , t h e AD9865 accep t s al l t h e clo c k and c o n t r o l sig n als f r o m t h e dig i t a l as i c . b e c a us e t h e s a m p ling clo c ks fo r t h e d a c and ad c a r e der i ve d i n ter n a l ly f r o m th e os ci n sig n al , t h e t x cl k an d r x c l k sig n als m u st be a t e x a c tl y t h e sa m e f r eq uen c y a s th e o s c i n s i gn al . th e phas e r e l a t i o n shi p s am o n g t h e t x clk, r x cl k, an d os cin sig n als ca n be arb i tra r y . i f t h e dig i tal as i c cann o t p r o v ide a lo w ji t t er c l o c k s o urce t o osci n, us e the AD9865 to g e n e ra te t h e clo c k fo r i t s d a c a nd ad c, and to p a ss t h e desir e d clo c k sig n a l t o th e d i g i tal a s i c via c l k o ut 1 o r c l k o ut2.
AD9865 rev. a | page 24 of 48 to tx digital filter 10 adio [9:0] oscin rxen AD9865 from rx adc 10 rxen txen txen txclk rxclk dac_clk adc_clk clkout digital asic 4493-0-009 tx/rx data[9:0] f i g u re 51. e x a m pl e of a h a lf -d up lex d i g i t a l inte r f ace wit h a d 98 65 s e r v i n g as t h e sl ave f i gur e 52 sh o w s a half-d u p lex in t e r f ac e wi t h t h e AD9865 ac t i ng as t h e mas t er , gen e ra t i n g al l t h e r e q u ir e d clo c ks . clk o ut1 p r o v i d es a c l ock eq ual t o th e b u s da ta ra t e tha t is f e d t o th e as i c as w e l l as bac k t o t h e t x clk and r x cl k in p u ts. this in t e r f ace has t h e ad van t a g e o f r e d u cing t h e dig i t a l as i c s p i n co un t b y t h r e e . the as i c n e e d s o n ly t o gen e ra te a b u s con t r o l sig n al tha t co n t r o ls th e da t a f l o w o n t h e b i dir e c t io nal b u s. to tx digital filter 10 adio [9:0] tx / r x d a t a [9 :0 ] clkout1 AD9865 from rx adc 10 rxen txen bus_ctr txclk rxclk clkin digital asic 4493-0-010 oscin from crystal or master clk f i g u re 52. e x a m pl e of a h a lf -d up lex d i g i t a l inte r f ace with ad 98 6 5 s e r v i n g as the m a ste r f u ll -duplex mode the f u l l -d u p lex m o de i n t e r f ace is s e le c t e d w h en t h e mo d e p i n is t i e d h i g h . i t c a n b e us e d fo r f u l l - o r ha lf-d u p l e x a p plic a t io n s . the d i g i t a l i n ter f ace p o r t is divi de d i n to tw o 6- b i t p o r t s ca l l e d t x [5:0] a n d rx[5:0], allo win g sim u l t a n eo us tx a nd rx o p er a - t i o n s f o r f u l l - d u p l e x ap p l i c at i o n s . in h a l f - d u p l e x ap p l i c at i o n s , th e tx[5:0] p o r t ca n als o be us e d t o p r o v ide a f a s t u p da t e o f t h e rxpga (ad98 75 b a ckwa r d -com p a t i b l e) d u r i ng a n rx o p era - t i o n . t h is fe a t ur e is ena b le d b y defa u l t an d ca n b e us e d to r e d u ce t h e r e q u ir e d p i n co u n t of t h e as ic (r efer t o rxpga c o n t r o l s e c t ion fo r det a i l s). i n e i t h er a p pli c a t io n, tx a nd rx d a t a a r e t r a n sfe r r e d b e tw e e n th e as i c an d AD9865 in 6 - b i t ( o r 5-b i t) nib b l es a t twice th e i n te r n a l i n put / out p ut word r a te s of t h e tx i n te r p ol a t i o n f i lte r a nd ad c . n o te t h a t t h e tx d a c u p da te r a te mu s t n o t be le s s t h a n t h e nib b l e ra t e . ther efo r e , t h e 2 o r 4 in ter p ola t io n f i l t er m u st b e us e d w i t h a f u l l - d u p lex in t e r f ace. the AD9865 ac ts as t h e mast er , p r o v idin g r x clk as a n ou t p u t c l oc k th a t i s use d f o r th e tim i n g o f bo th t h e t x [5: 0 ] a n d r x [5: 0 ] p o r t s. r x c l k a l wa y s r u n s a t t h e nib b l e r a te and can b e i n ver t e d o r dis a b l e d v i a an s p i r e g i ster . b e ca us e r x clk i s der i ve d f r o m th e c l ock syn t h e si z e r , i t r e m a in s a c ti v e , p r o v id ed th a t th i s fun c - t i on a l bl o c k re m a i n s p o we re d on . a bu f f e r e d ve r s i o n of t h e s i g n a l ap p e a r i n g at o s c i n c a n a l s o b e d i r e c t e d t o r x c l k by s e t t in g bi t 2 o f reg i st er 0x05. this f e a t ur e al lo ws the AD9865 t o b e com p letely p o w e r e d do w n (i n c l u ding t h e clo c k sy n t h e s i zer ) w h i l e s e r v i n g as t h e mas t er . the tx[5:0] p o r t o p era t es in t h e fol l o w in g ma nn er wi t h t h e sp i r e g i s t er def a u l t s e t t in gs. t w o co n s e c u t i v e ni bb le s o f t h e tx da t a a r e m u l t i p lexe d to get h er to fo r m a 10- b i t da t a - w o r d in tw o s c o mp l e m e n t f o r m at . t h e c l o c k ap p e a r i n g o n t h e r x c l k p i n i s a b u f f er e d v e rsi o n o f t h e in t e r n al clo c k us e d b y t h e tx[5:0] p o r t s in p u t l a t c h w i t h a f r e q ue n c y t h a t is a l wa y s tw ice t h e ad c s a m p le ra te (2 f ad c ). da ta f r o m t h e tx[5:0] p o r t is r e ad o n t h e ri s i n g edg e o f this s a m p ling c l o c k, as il l u s t ra ted in t h e t i min g d i ag r a m s h ow n i n fi g u re 5 3 . n o te, tx q u i e t mu s t r e m a i n h i gh f o r th e r e co n s tr uct e d t x da ta t o a p p e a r a s a n a n alog si gn al a t t h e output of t h e t x d a c or i a m p . t x2l s b t x0l s b t su t h d t ds t dh rxclk txsync tx[5:0] 4493-0-011 t x1m s b t x1l s b tx 2 m s b t x3l s b tx 3 m s b f i gure 53. t x [5: 0 ] p o r t f u l l - d u p l ex t i mi ng d i agr a m th e t x sy nc s i g n a l i s u s e d to i ndi c a te to w h i c h word a n i bbl e b e lo n g s. w h ile t x s y nc is lo w , th e f i rst ni bb le o f e v er y w o r d i s r e ad as t h e m o st sig n if ican t n i bb le. t h e s e con d nib b l e o f t h a t s a m e w o r d is r e ad o n t h e f o l l o w in g t x s y n c hig h leve l as t h e le ast sig n if ica n t nib b l e . i f t x s y n c is lo w fo r mo r e t h a n o n e c l oc k c y c l e , th e la s t tra n smi t da ta i s r e a d co n t in uo us l y un til t x s y n c i s b r o u gh t hi gh f o r th e sec o n d ni b b l e o f a n e w tra n s - mi t w o r d . this fea t ur e can b e us ed t o f l us h t h e in t e r p ola t o r f i l t ers wi th zer o s. n o t e tha t t h e gain sig n al m u s t be kep t lo w du r i n g a t x o p e r a t i o n . the rx[5:0] p o r t o p era t es in t h e fol l o w in g ma nn er wi t h t h e sp i r e g i s t er def a u l t s e t t in gs. t w o co n s e c u t i v e ni bb le s o f t h e rx da t a a r e m u l t i p lexe d to get h er to fo r m a 10- b i t da t a - w o r d in tw o s co m p le m e n t f o rma t . th e rx da t a is valid o n the r i sin g e d g e o f r x clk , a s il l u st ra t e d in t h e t i m i n g dia g ra m sh o w n in f i g u re 5 4 . th e r x s y nc s i g n a l i s u s e d to i ndi c a te to w h i c h word a n i bbl e b e lo n g s. w h ile r x s y nc is lo w , th e f i rst ni bb le o f e v er y w o r d i s t r ans m it te d a s t h e mo st s i g n i f i c an t n i bbl e. t h e s e c o n d n i bbl e of th a t sa m e w o r d i s tra n sm i t t e d o n t h e f o llo w in g r x s y n c h i g h le vel as t h e le ast sig n if ican t n i b b le.
AD9865 rev. a | page 25 of 48 4493-0-012 rxclk rxsync rx[5:0] rx 0ls b r x 1m s b r x1l s b rx2 m sb rx3 l sb r x3m sb t dv t dh f i g u re 54. f u ll-d u p l ex r x p o r t ti mi ng t o add f l exi b ili t y t o th e f u l l -d u p lex dig i t a l in t e r f ace p o r t , s e veral p r og ra mmin g op t i o n s a r e a v a i lab l e in t h e s p i r e g i s t ers. th es e o p t i o n s a r e lis t e d i n t a b l e 14. th e t i mi n g fo r t h e tx[5:0] a nd/or rx [ 5 :0] p o r t s ca n b e i n d e p e nde n t ly cha n ge d b y s e le c t in g e i t h er t h e r i s i ng or f a l l i ng cl o c k e d ge a s t h e s a m p l i ng / v a l i d a t i n g e d ge o f th e c l o c k. i n ver t in g r x clk ( v ia b i t 1 o r reg i s t er 0x05) a f f e ct s bo th t h e r x a n d t x in t e r f a c e , beca use t h ey bo t h use rx c l k . table 14. spi registers for full-duplex inter f ace a ddress (he x ) b i t d e s c r i p t i o n 0x05 (2) oscin to rx clk (1) i n v e r t rx clk (0) dis a b l e r x clk 0x0b (2) rx gain on t x por t 0 x 0 c ( 4 ) i n v e r t t x sy nc (3) t x 5/ 5 nibbl e (2) ls nibble first (1) t x clk nega tiv e edge (0) t w os complemen t 0x0d (5) rx por t thr e e - s t a t e (4) i n v e r t r x sy nc (3) rx 5/ 5 nibbl e (2) ls nibble first (1) r x clk nega tiv e edge (0) t w os complemen t 0x0e (7) l o w driv e s t r e ngth the def a u l t tx a nd rx da t a i n pu t fo r m a t s a r e t w o s co m p lem e n t , b u t ca n b e change d to st r a ig h t b i na r y . t h e de fa u l t t x s y n c and r x s y nc s e t t i n gs ca n b e chan ge d such t h a t t h e f i rst nib b l e o f t h e w o r d a p p e ars w h ile t x s y n c , r x s y n c , o r bo t h a r e hig h . als o , t h e l e ast si g n if ica n t ni bb le ca n b e s e le c t e d as t h e f i rst nib b l e o f t h e w o r d (ls nib b l e f i rs t). th e o u t p ut dr i v er s t r e n g t h ca n a l s o b e r e d u ce d fo r lo w e r da t a r a te a p pli c a t i o n s . f o r th e AD9865 , th e m o st sig n if ica n t ni bb le def a u l ts t o 6 b i ts, a nd t h e le ast sig n if ican t n i bb le defa u l ts to 4 b i t s . this can b e cha n ge d s o t h a t t h e le a s t sig n if i c a n t nib b l e an d m o st sig n if ican t nib b l e ha v e 5 b i ts eac h . t o accom p li sh th i s , s e t th e 5/ 5 ni b b le b i t in reg i st er 0x0c a nd reg i st er 0x0d a nd us e da ta p i n s tx[5:1] a n d rx[5:1]. f i gur e 55 sh o w s a p o ssib le d i g i t a l in t e r f ace b e t w e e n an as i c a nd t h e ad986 5. the AD9865 s e r v es as th e mas t er g e nera tin g t h e r e quir e d clo c ks fo r t h e as ic. this in ter f ac e r e q u ir es t h a t t h e as i c r e s e r v e 16 p i n s fo r t h e in ter f ace , as s u mi ng a 6-b i t nib b l e wid t h an d t h e us e o f t h e tx p o r t fo r rxpga ga in co n t r o l . n o t e tha t t h e as i c p i n al lo c a tio n can be r e d u ced b y 3, if a 5-b i t nib b l e wi d t h is us e d an d t h e ga in (o r ga in st r o b e ) o f t h e rxpg a i s co n t r o ll ed via th e s p i po r t . to tx digital filter 10/12 AD9865/ad9866 from rxadc 10/12 rxsync txsync tx_sync rxclk clkout1 clkout2 clkin digital asic 4493- 0- 013 oscin from crystal or master clk gain optional tx data[5:0] r x d a ta [5 :0 ] r x [5 :0 ] rx_sync mux demux t x [5 :0 ] 6 to rxpga f i g u re 55. e x a m pl e of a f u l l -d up lex d i g i t a l inte r f ace wi th o p tio n al rxpg a g a i n co nt r o l via t x [ 5 :0 ] rxpga c o ntr o l the AD9865 con t a i n s a dig i tal pga in t h e rx p a th tha t is us e d to ex tend t h e d y na mic r a n g e. t h e rx p g a can b e p r o g r a mme d o v er ?12 db t o +48 db wi t h 1 db r e s o l u tio n usin g a 6-b i t w o r d , a nd wi t h a 0 db s e t t in g co r r esp o ndin g to a 2 v p - p in p u t sig n a l . the 6- b i t w o rd is fe d in t o a l u t t h a t is us e d t o dist r i b u t e t h e desir e d ga i n o v e r t h r e e a m plif ic a t io n st a g es w i t h in t h e rx p a t h . u p o n p o w e r - u p , t h e rxpga ga in r e g i s t er is s e t t o i t s minim u m ga in o f ?12 db . th e rxpga ga in ma p p in g i s sho w n in f i gur e 56. t a b l e 15 lis t s t h e s p i r e g i s t ers p e r t a i nin g t o t h e rxpga.
AD9865 rev. a | page 26 of 48 4493-0-014 6-bit digital word-decimal equivalent gain ( d b) 0 48 24 60 66 ?12 ?6 0 6 12 18 24 30 36 42 54 42 48 30 36 61 2 18 f i g u re 56. d i g i t a l g a in m a p p ing of r x pg a table 15. spi registers rxpga control a ddress (he x ) b i t d e s c r i p t i o n 0x09 (6) enable rxpga upda t e via spi ( 5 : 0 ) rxpga gain c o de 0x0b (6) s e lec t t x pga vi a pga[5:0] (5) s e lec t rxpga via pga[5:0] ( 3 ) enable s o f t w a r e gain str obe C f u ll- d u plex (2) enabl e rx pga upda t e via t x [5:0] C f u l l - dupl ex (1) 3-bit rxpga gain mapping C half- d uplex the rx pga gai n r e g i ster can b e u p da te d v i a t h e tx [ 5 :0] p o r t , th e pga[5:0] p o r t , o r th e s p i p o r t . th e f i rst two m e t h o d s al lo w f a st u p d a te s of t h e r x p g a g a i n re g i ste r and s h ou l d b e co n s ider e d fo r dig i t a l a g c f u nc t i o n s r e q u ir i n g a fast clo s e d - lo o p r e s p o n s e . the s p i p o r t al l o ws dir e c t u p da t e an d r e ad b a c k o f th e r x p g a ga i n r e gi s t e r via r e gi s t e r 0 x 0 9 wi th a n u p da t e r a te l i mite d to 1 . 6 m s p s ( w i t h s c l k = 3 2 m h z ) . n o te t h a t bit 6 of r e g i st e r 0 x 0 9 m u st b e s e t f o r a re a d or w r ite op e r a t i o n . u p d a ti n g th e r x p g a v i a th e t x [ 5 : 0 ] po rt i s a n o p t i o n o n l y i n full - d u p l e x m o d e 1 . i n this cas e , a hig h leve l o n t h e g a in p i n, 2 wi t h t x s y n c l o w , p r og ra m s t h e pga s e t t in g on ei t h er t h e r i s i ng e d ge or f a l l i n g e d ge of r x c l k , a s s h ow n i n fi g u re 5 7 . the gai n p i n m u s t be h e l d hig h , t x s y n c m u s t be he ld lo w , a nd gai n da t a m u st b e st a b le fo r o n e o r m o r e clo c k c y cles to up d a t e t h e r x p g a g a i n s e tt i n g . a lo w le ve l o n t h e g a in p i n e n a b les da t a t o be f e d t o the dig i ta l in t e r p ol a t ion f i l t er . this i n ter f a c e sh o u ld b e con s ider e d w h en u p g r adin g exis t i n g desig n s f r o m th e ad9875/ad9876 mxfe p r o d uc ts o r half -d u p lex a p p l ic a t io n s tr yin g t o minimize an as i c s p i n coun t. t su rx c l k t x syn c tx [ 5 : 0 ] t hd ga in ga i n 4493-0-015 f i g u re 57. u p dat i n g r x pg a v i a t x [5: 0 ] i n f u ll -d uplex m o de u p d a ti n g th e r x p g a ( o r t x p g a ) v i a th e p g a [ 5 : 0 ] po rt i s a n opt i on f o r b o t h t h e h a l f - d u pl e x 3 a nd f u l l -d u p lex in ter f ace. the pga p o r t co n s is ts o f a n in p u t b u f f er tha t p a s s es th e 6 - b i t da ta a p p e a r in g a t i t s in p u t d i r e c t ly t o t h e rxpga (o r txpga) ga i n re g i ste r w i t h no g a t i ng s i g n a l re qu i r e d . b i t 5 or bi t 6 of reg i st er 0x0b is us e d t o s e le c t w h et h e r t h e da t a u p da t e s t h e rxpga o r txp g a ga in r e g i st e r . i n a p plic a t io ns t h a t s w i t ch be tw e e n rxpg a a nd txpga g a in con t r o l v i a pga[5:0], be ca r e f u l t h a t t h e rxpga (o r txp g a) is n o t ina d v e r t en t l y lo ade d w i th t h e w r o n g da ta d u ri n g a tra n si ti o n . i n t h e ca se o f a n rxpga t o txp g a t r a n si t i on, f i rs t de s e le c t t h e rxpga ga i n r e g i s t er , u p da t e t h e pga[5:0] p o r t wi t h t h e des i r e d txpg a ga in s e t t i n g , a n d th e n se l e ct th e t x pg a g a i n r e gi s t e r . t h e rxpga als o o f f e r s a n al t e r n a t i v e 3- b i t w o r d ga i n m a p p i n g opt i on 4 t h at p r o v ides a ? 1 2 db t o + 3 6 db s p an in 8 db inc r emen ts as s h o w n in t a ble 16. th e 3-b i t w o r d is dir e c t ed t o p g a [ 5 : 3 ] wi t h pga [ 5] b e in g t h e ms b . th is f e a t ur e is back w a r d - c o m pa t i b l e wi th th e ad 99 75 m xfe a n d al l o w s di r e ct i n t e rfac in g t o th e cx116 47 o r i n t5 130 h o mepl u g 1. 0 p h ys . table 16. pga timing for ad9975 backward-compatible mode digital ga in s e tting pga[5:3 ] decimal g a in (db) 0 0 0 0 ?12 0 0 1 1 ? 1 2 010 2 ? 4 011 3 4 100 4 1 2 1 0 1 5 2 0 1 1 0 6 2 8 1 1 1 7 3 6 1 d e fa u l t s e t t i n g for ful l - d upl e x m o de ( m od e = 1 ) . 2 th e g a in st robe ca n a lso be set i n so ft wa re vi a r e g. 0x0b, bi t 3 fo r continuous upd a ting. this el iminates the requirement f o r external gain s i gnal , red u cing the as ic pin co unt by 1. 3 d e fa u l t s e t t i n g for h a lf- duple x m o de ( m od e = 0 ) . 4 d e fa u l t s e t t i n g for mod e = 0 a n d con fig =1.
AD9865 rev. a | page 27 of 48 txpg a c o n t rol the AD9865 als o co n t a i n s a dig i tal pg a in t h e tx p a th dis t r i - b u te d b e tw e e n t h e tx d a c and i a mp . t h e tx p g a is us e d to co n t r o l t h e p e a k c u r r en t f r o m t h e txd a c and i a mp o v er a 7.5 db an d 19.5 db s p a n , r e sp ec ti v e l y , wi th 0.5 db r e s o l u tio n . a 6-b i t w o r d is us e d t o s e t t h e txpga a t t e n u a t io n acco r d in g to th e ma p p in g sho w n in f i gur e 5 8 . the tx d a c ga in ma p p i n g is a p p l ic a b le o n l y when b i t 0 o f reg i s t er 0x0e is s e t, an d onl y the f o ur ls bs o f th e 6-b i t ga in w o r d a r e r e levan t . 04493-0-063 6-bit digital code (decimal equivalent) tx atte nuation (dbfs ) 0 8 16 24 32 40 48 56 64 0 ?20 ?16 ?18 ?14 ?12 ?10 ?8 ?6 ?2 ?4 ?1 ?17 ?19 ?15 ?13 ?11 ?9 ?7 ?3 ?5 txdacs ioutp output has 7.5db range iamps ioutn and ioutg outputs has 19.5db range f i g u re 58. d i g i t a l g a in m a p p ing of t x p g a the txpg a r e g i s t er can b e u p da t e d v i a t h e pg a[5:0] p o r t o r s p i p o r t . th e f i rs t met h o d sh ou ld b e co n s idere d fo r fas t u p da t e s o f t h e txpga reg i s t er . i t s o p era t io n is simi la r to t h e de s c r i p t io n in t h e rxpga c o n t r o l s e c t ion. the s p i p o r t a l lo ws dir e c t u p - da t e and r e ad b a ck o f t h e txpg a r e g i s t er vi a r e g i s t er 0x0a wi t h a n u p da t e r a t e l i mi t e d t o 1.6 ms ps (sclk = 32 mh z). b i t 6 o f reg i st er 0x0a m u s t b e s e t fo r a r e ad o r wr i t e o p era t ion. t a b l e 17 lis t s t h e s p i r e g i s t ers p e r t a i nin g t o t h e txpga. th e t x p g a c o n t ro l re g i ste r d e f a u l t s e tt i n g i s f o r m i n i m u m a t t e n u a t io n (0 db fs) wi th t h e p g a[5:0] p o r t dis a b l ed f o r tx ga in co n t r o l . table 17. spi r e gisters txpga control a ddress (he x ) b i t d e s c r i p t i o n 0x0a (6) enable t x pga upda t e via spi ( 5 : 0 ) t x pga gain c o de 0x0b (6) s e lec t t x pga vi a pga[5:0] ( 5 ) s e lec t rxpga via pga[5:0] 0x0e (0) t x d a c outpu t (i a m p dis a bl ed)
AD9865 rev. a | page 28 of 48 transmit pa th the AD9865 (or ad9866) tra n smi t p a t h co n s ists o f a s e lec t a b le dig i tal 2/4 in t e r p ola t ion f i l t er , a 10-b i t o r 12-b i t txd a c, an d a c u r r en t-ou t p ut a m plif ier (i a m p) as sho w n i n f i gur e 59. n o t e t h a t t h e a d d i t i on a l t w o bit s of re s o lut i on of f e re d b y t h e a d 9 8 6 6 r e su l t in a 10 db to 12 db r e d u c t io n i n t h e p a ss - b a nd n o is e f l o o r . th e d i g i t a l in t e r p ol a t ion f i l t er r e l a xes t h e tx a n a l og f i l t e r i n g r e q u i r em en t s b y s i m u l t a n eo us l y r e d u cin g t h e i m a g e s f r o m t h e d a c r e co n s t r uc t i o n pr o c es s w h i l e i n c r e a sin g t h e a n alog f i l t er s t r a n si t i on b a n d . the dig i t a l i n t e r p ola t ion f i l t er c a n a l s o b e b y p a ss e d , re su l t ing in l o we r dig i t a l c u r r e n t co n s um p t io n. 10 ad986 5/ad 9 8 6 6 0 to ?7.5db 4493-0-017 0 to ? 12db 2-4x io u t _ g + io u t _ n + io u t _ n ? io u t _ g ? iamp iou t _p+ iou t _p ? tx c l k t xen / syn c a d i o [ 1 1 :6 ]/ t x [5 :0 ] a d i o [ 1 1 :6 ]/ r x [5 :0 ] txdac f i g u re 59. f u nc t i o n al bl ock d i ag r a m o f t x p a t h digit a l in t e rpol a t i o n fil t ers the in p u t da t a f r o m the tx p o r t ca n be f e d in t o a s e le c t a b le 2/4 in t e r p ol a t io n f i l t er o r dire c t ly in t o t h e t x d a c (fo r a ha lf- d u plex o n l y ). th e in t e r p ola t ion fac t o r fo r t h e di g i t a l f i l t er is s e t v i a sp i r e g i s t er 0x0c wi t h t h e s e t t in gs sh o w n i n t a b l e 18. th e max i m u m i n p u t w o r d ra te, f da t a , in t o t h e i n t e r p ola t ion f i l t er is 80 ms ps; t h e maxim u m d a c u p da te ra t e is 20 0 ms ps. th er e- fo r e , a p plica t io ns w i t h in pu t w o r d ra t e s a t o r b e lo w 50 ms ps ca n b e n e f i t f r o m 4 in t e r p ola t io n, w h i l e a p pli c a t io ns w i t h i n pu t w o r d r a tes b e twe e n 50 ms ps and 80 ms ps can b e n e f i t f r o m 2 in t e r p ol a t ion. table 18. i n ter p olation factor set via spi re gister 0x0c bits [7:6] in t e rpola t ion f a c t or 00 4 01 2 10 1 (hal f- dupl ex onl y ) 11 do not use the i n ter p ol a t i o n f i l t er co n s ist s o f tw o cas c ade d ha lf-b and f i l t e r s t a g es w i t h e a ch s t a g e p r o v i d i n g 2 in t e r p ol a t ion. th e f i rst s t a g e f i l t er co n s is ts o f 43 t a ps. th e s e con d st a g e f i l t er , o p era t i n g a t t h e hig h er da ta ra te , co n s is ts o f 11 ta ps. th e n o r m alize d wi deb a n d and p a ss-b and f i l t er r e sp o n s e s (r ela t ive f da t a ) f o r th e 2 a n d 4 lo w- p a ss in ter p ola t i o n f i l t ers a r e sho w n i n f i gur e 6 0 and f i g u re 6 1 , re sp e c t i v e ly . the s e re sp ons e s a l s o incl u d e th e i n h e r e n t sin c (x) f r o m th e t x d a c r e co n s tr ucti o n p r oce s s a n d ca n be us e d t o es tima t e an y p o st a n alog f i l t er ing r e q u ir emen ts. the p i p e l i n e del a ys o f th e 2 and 4 f i l t er r e s p o n s e s a r e 21.5 and 2 4 cl o c k c y cl es , resp e c t i vel y , rel a t i ve to f da t a . th e f i l t er dela y is a l s o t a k e n in to co n s idera t ion fo r a p plica t io n s co nf igur e d fo r a half-d u p lex in te r f ace w i t h t h e half-d u plex p o w e r - do wn mo de ena b le d. this fe a t ur e al lo ws t h e us er t o s e t a p r og ra mma b l e dela y t h a t p o w e rs do w n t h e tx d a c and i a mp o n ly a f ter t h e las t tx in p u t s a m p le has p r o p aga t e d t h r o ug h t h e dig i tal f i l t er . s e e t h e p o wer c o n t r o l an d dissi p a tio n s e c t ion fo r m o r e deta il s. 4493-0-018 normalized frequency (relative to f data ) wide band response (db) 0 10 1.25 2.00 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 1.75 0.75 1.00 1.50 wide band 0.50 0.25 pass band response (db) 2.5 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 2.0 pass band ?1.0db @ 0.441 f data f i g u re 60. f r equen c y r e s p ons e of 2 i n terpol at i o n f i lte r (nor ma li zed to f da t a ) 4493-0-019 normalized frequency (relative to f data ) wide band response (db) 0 10 2.5 4.0 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 3.5 1.5 2.0 3.0 wide band 1.0 0.5 pass band response (db) 2.5 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 2.0 pass band ? 1.0db @ 0.45 f data f i g u re 61. f r equen c y r e s p ons e of 4 i n terpol at i o n f i lte r (nor ma li zed to f da t a ) txd a c a n d iamp arc h i t ec ture the tx p a t h con t a i n s a tx d a c wi t h a c u r r en t a m plif ier , i a mp . the tx d a c r e c o n s t r uc ts t h e o u t p u t o f t h e in t e r p ola t ion f i l t er a nd s o ur ces a di f f er en t i a l c u r r en t o u t p u t t h a t c a n b e d i r e c t e d to a n ext e r n a l lo ad o r fe d in t o t h e i a mp fo r f u r t h e r a m plif ica t io n. the tx d a c s and i a mps s p e a k c u r r en t o u t p u t s a r e dig i tal l y p r og ra mma b l e o v er a 0 t o ?7.5 db an d 0 t o ?19 . 5 db ra n g e , re sp e c t i v e ly , i n 0 . 5 db i n c r e m e n ts . n o te t h a t t h is assu me s defa u l t r e g i s t er s e t t in gs f o r reg i s t er 0x10 a nd reg i s t er 0x11.
AD9865 rev. a | page 29 of 48 a p pl i c a t i o ns d e m a n d i ng t h e h i g h e s t sp e c t r a l p e r f or m a nc e a nd/o r lo w e st p o w e r co n s u m p t i o n can us e t h e tx d a c o u t p u t d i r e ctl y . th e t x d a c i s ca pa b l e o f d e l i v e rin g a p e ak s i gnal po w e r - u p t o 10 d b m wh ile m a in ta in i n g r e spect a b l e lin e a r i t y p e r f or m a nc e, a s sh o w n i n fi g u re 2 7 t h rou g h fi g u re 3 8 . f o r p o w e r - s e n s i t i v e a p plic a t io n s r e q u ir in g t h e hi g h est tx p o w e r ef f i cien c y , t h e txd a c s f u l l -s c a le c u r r en t o u t p ut ca n b e r e d u ce d t o as lo w as 2 m a , a nd i t s lo ad resist o r s size d t o p r o v id e a sui t ab le vol t a g e swi n g t h a t can b e am plif ie d b y a lo w- p o w e r o p - a m p-b a s e d dr i ver . m o st a p plic a t ion s r e q u ir ing hig h er p e a k sig n a l p o w e rs (u p t o 23 db m) sh o u ld co n s ider usin g th e i a mp . th e i a mp can b e co nf igur e d as a c u r r en t s o ur ce fo r lo ads ha vi n g a w e l l def i n e d im p e dan c e (50 ? o r 75 ? s y s t em s), o r a v o l t a g e s o ur ce (wi t h t h e a d d i t i o n of a p a i r of n p n t r ans i s t or s ) f o r p o or ly d e f i ne d l o a d s h a v i ng v a r y i n g i m p e d a nc e ( s u c h a s p o we r l i ne s ) . fi g u r e 6 2 s h ow s t h e e q u i v a l e nt s c h e m a t i c o f t h e t x d a c a n d i a mp . th e tx d a c p r o v i d es a dif f er en t i al c u r r e n t o u t p u t a p p e a r in g a t i o u t p+ a nd iou t p?. i t can b e m o dele d as a dif f er en t i a l c u r r en t s o ur ce ge n e r a t i n g a sig n a l - d ep e nden t ac cu rr e n t , wh en ? i s has a p e a k c u r r en t o f i alo n g wi th tw o dc cu rr e n t so u r c e s , so u r c i n g a s t andin g c u r r en t eq ual t o i. the f u l l - s c ale o u t p u t c u r r en t, io utfs, i s e q ual t o t h e s u m o f t h e s e s t an din g c u r r en t so ur ces (i o u t f s = 2 i). 4493- 0- 020 n (i+ ? i) n (i ? ? i) g (i+ ? i) g (i ? ? i) ioutn? ioutn+ iout g ? iout g+ ? i s i i txdac refadj refio ioutp+ ioutp? i + ? i i? ? i i off1 r set 0.1 f i off1 i off2 xg xg xn xn i off2 iamp f i g u re 62. equiv a le nt s c h e m a t i c of t x da c and ia m p the val u e o f i is det e r m i n e d b y t h e r set val u e a t t h e ref a d j p i n a l o n g w i th th e t x pa th s d i gi t a l a t t e n u a t i o n se t t i n g. w i t h 0 db a t t e n u a t ion, t h e val u e o f i is i = 16 (1.23 /r set ) ( 1 ) f o r e x am pl e, an r set val u e o f 1.96 k? r e s u l t s in i eq ual t o 10.0 ma wi th i o utfs eq ual to 20.0 ma. n o te tha t t h e refi o p i n p r o v ide s a no mina l b a nd ga p r e fer e n c e vol t a g e o f 1.23 v a nd sh o u ld be deco u p led t o a n a l og g r o u n d via a 0.1 f ca p a ci t o r . the dif f er en t i al c u r r en t o u t p u t o f t h e txd a c i s al wa ys co n- ne c t e d to t h e iou t p pi ns , b u t c a n b e d i re c t e d to t h e i a m p b y c l ea r i n g b i t 0 o f reg i st er 0x0e. a s a r e s u l t , t h e i o utp p i n s mu s t r e ma in com p lete l y o p en, i f t h e i a mp is t o b e us e d . th e i a mp co n t a i n s tw o s e ts o f c u r r en t mir r o r s t h a t a r e us e d t o r e plica t e t h e txd a c s c u r r en t ou t p ut w i t h a s e l e c t a b le ga i n . the f i rst s e t o f c u r r en t mir r o r s is desig n a t e d as t h e p r ima r y p a t h , pro v i d i n g a g a i n f a c t or of n t h a t i s pro g r a m m a bl e f r om 0 to 4 i n s t eps o f 1 via b i ts 2:0 o f reg i st er 0x10 wi t h a defa u l t s e t t in g o f n = 4. b i t 7 o f t h is r e g i s t er mu s t b e s e t t o o v er wr i t e t h e defa u l t s e t t in gs o f t h is reg i s t er . this dif f er en t i al p a t h ex hib i ts t h e b e s t l i n e ar it y p e r f or m a nc e ( s e e fi g u re 4 2 ) and i s a v a i l a bl e a t t h e i o ut n+ an d iout n? p i ns. t h e m a x i m u m p e a k c u r r en t p e r o u t p u t is 100 ma a nd o c c u rs w h en t h e txd a c s s t an din g c u r r en t, i, is s e t f o r 12.5 ma (i o u tfs = 25 ma) . the s e cond s e t o f c u r r en t mir r o r s is desig n a t e d as t h e s e co n- d a r y p a t h prov i d i n g a g a i n f a c t or of g t h a t i s pro g r a m m a bl e f r o m 0 t o 36 via b i ts 6:4 o f reg i s t er 0x10 a nd b i ts 6:0 o f reg i st er 0x11 wi t h a def a u l t s e t t in g o f g = 12. this dif f er en tial p a t h is in te nde d to b e us e d i n t h e vol t a g e m o d e co nf i g ur a t io n to b i a s t h e ext e r n al np n tra n sis t o r s, b e ca us e i t exhi b i ts deg r ade d l i n e ar it y p e r f or m a nc e ( s e e fi g u re 4 3 ) rel a t i v e t o t h e pr i m ar y p a th. i t is ca p a ble o f sinkin g u p t o 180 ma o f p e ak c u r r en t in t o ei t h er i t s i o utg+ o r i o ut g? p i n s . the s e conda r y p a th ac t u al l y co n s is ts o f thr e e ga in s t a g es (g1, g2, and g3), whic h a r e indivi d u al l y p r og ra mma b l e as s h o w n in t a ble 19. w h i l e ma n y p e r m u t a t i o n s ma y exist t o p r o v id e a f i xe d ga in o f g, t h e line a r i t y p e r f o r ma n c e o f a s e conda r y p a t h r e m a in s r e la t i vely i n d e p e nd e n t of t h e v a r i ou s i n d i v i d u a l g a i n s e tt i n g s t h a t are p o ssi b le t o achi e v e a p a r t ic u l a r o v era l l ga in fa c t o r . b o t h s e t s of m i r r or s s i n k c u r r e n t , b e c a u s e t h e y or i g i n a t e f r om nmos de v i ces. ther efo r e , e a ch o u t p ut p i n r e q u ir es a dc c u r r en t pa th t o a pos i ti v e s u p p l y . a l th o u gh th e v o l t a g e o u t p u t o f ea c h o u t p u t p i n can s w in g betw een 0. 5 v a nd 7 v , o p t i m u m ac p e r - f o r m a n ce is typ i cal l y ac hieved b y limi tin g t h e ac v o l t a g e s w ing wi t h a dc b i a s vol t a g e s e t b e tw e e n 4 t o 5 v . l a st ly , b o t h t h e st an d i n g c u r r en t, i, an d t h e ac c u r r en t, ?i s , f r o m t h e txd a c ar e a m plif ie d b y t h e ga in fac t o r (n a nd g) w i t h t h e t o t a l st an d i n g c u r r en t dr a w n f r o m t h e p o si t i ve su p p ly b e in g e q ua l to 2 ( n = g ) i p r og ra mma b l e c u r r en t s o ur ces i o ff1 and i o ff2 via reg i s t er 0x12 ca n b e us e d to i m p r o v e t h e p r i m a r y a n d s e conda r y p a t h m i r r or s l i ne ar i t y p e r f or m a nc e u n d e r c e r t ai n c o nd i t i o n s b y i n cr ea si n g t h ei r s i gn al - t o-s t a n d i n g curr e n t ra tio . t h i s f e a t ur e p r o v i d es a m a r g i n al im p r o v em en t in d i s t o r ti o n pe rf o r m a n c e un der la rg e sig n al co ndi t i o n s w h e n t h e p e ak ac c u r r en t o f t h e r e co n s t r uc te d w a vefo r m f r e q uen t ly a p p r o a ch es t h e dc st andi n g c u r r en t w i t h in t h e txd a c (0 t o ?1 dbfs si n e w a v e ) c a usin g t h e in t e r n a l mir r o r s t o t u r n o f f. h o w e v e r , t h e im p r o v emen t in dis t o r t i o n p e r f o r ma n c e di mini sh es as t h e cr est fac t o r (p e a k-t o - r m s ra tio) o f the ac sig n al in cr e a s e s. m o s t a p p l ica t io ns can dis a b l e t h e s e c u r r en t s o ur ces (s et t o 0 ma v i a r e g i s t er 0x12) t o r e d u ce t h e i a m p s c u r r en t co n s um p t ion.
AD9865 rev. a | page 30 of 48 table 19. spi registers for txdac and iamp a ddress (he x ) bit description 0 x 0 e ( 0 ) t x d a c o u t p u t 0x10 ( 7 ) enable cur r e n t mir r o r gain setti ngs ( 6 : 4 ) sec o ndar y pa th first stage gain of 0 to 4 with ? = 1 (3) not us ed ( 2 : 0 ) p r imar y pa th nmos gain of 0 t o 4 with ? = 1 0x11 (7) d o n t car e ( 6 : 4 ) sec o ndar y pa th sec o nd stage gain of 0 to 1.5 with ? = 0.25 (3) not us ed ( 2 : 0 ) sec o ndar y pa th thir d stage gain of 0 to 5 with ? = 1 0x12 (6:4) ioff2, sec o ndar y pa th standing cur r en t (2:0) ioff1, pr imar y pa th standing c u r r en t t x progr a mmable gain c o ntrol t x pga fun c ti o n ali t y i s also a v a i la b l e t o set t h e peak o u t p u t c u r r en t f r o m t h e txd a c o r i a mp . th e txd a c a nd i a m p a r e d i g i t a l l y pro g r a m m a bl e v i a t h e pg a[5: 0] p o r t or s p i o v er a 0 db t o ?7 . 5 db a n d 0 db t o ? 1 9 . 5 d b ra n g e , r e s p ec ti v e l y , in 0 . 5 d b inc r e m e n t s . the tx pg a can b e co n s id er e d as two cas c a d e d a t te n u a t o r s wi t h th e txd a c p r o v iding 7.5 db ran g e in 0.5 db incr em en ts, and th e i a mp p r o v idin g 12 db ra n g e in 6 db in cr em en ts. a s a re su l t , t h e i a m p s c o m p o s ite 1 9 . 5 db sp an is v a l i d on ly if reg i st er 0x10 r e ma in s a t i t s def a u l t s e t t ing o f 0x44. m o dif y in g t h is r e g i st er s e t t in g co r r u p ts t h e l u t and r e su l t s in an i n v a li d g a i n m a ppi ng . tx da c o u t p u t o p e r a t i o n the dif f er en t i al c u r r en t o u t p u t o f t h e txd a c i s a v a i la b l e a t t h e i o utp+ and ioutp? pin s and t h e i a mp sh ou ld b e dis a b l e d b y s e t t in g b i t 0 o f reg i s t er 0x0e. an y lo ad co nn ec ted t o t h es e p i n s m u s t be g r o u nd r e f e r e n c e d t o p r o v ide a dc p a th f o r th e c u r r en t s o ur ces. f i gur e 63 sh o w s th e ou t p u t s o f th e txd a c dr i v in g a doub ly ter m ina t e d 1: 1 t r a n sfo r m e r w i t h i t s ce n t er -t a p tied t o g r o u n d . the p e ak-t o-p e ak v o l t a g e , v p-p , acr o s s r l (a nd i o ut + t o i o ut ?) is eq ua l t o 2 i (r l // r s ). w i t h i = 10 ma a nd r l = r s = 50 ?, v p-p is eq ual t o 0.5 v wi t h 1 dbm o f p e a k p o w e r b e in g del i ver e d to r l and 1 dbm b e i n g di ssi p a t e d i n r s . 4493-0-021 ioutn? ioutn+ ioutg? ioutg+ iout_p+ iout_p ? 0 to ?7.5db 0 to ? 12db iamp re fio re fadj r set 0.1 f r s 1:1 r l txdac f i g u re 63. t x da c o u t p ut d i rec t ly v i a center - t ap t r a n s f or me r the tx d a c is c a p a b l e o f de li v e r i n g u p t o 10 db m p e a k p o w e r t o a lo ad , r l . t o in cr e a s e t h e p e a k p o w e r fo r a f i xe d st anding c u r r en t, on e m u s t in cr eas e v p-p acr o s s i o utp + a n d i o utp? b y i n c r e a s i ng o n e or more of t h e f o l l o w i n g p a r a me t e r s : r s , r l (if pos s i b le ), a n d / o r th e t u rn s ra tio , n , o f tra n sf o r m e r . f o r e x a m - pl e, t h e r e mo va l of r s a nd t h e u s e o f a 2:1 i m p e dan c e ra tio t r a n sfo r m e r in t h e p r e v io us exam ple r e s u l t s in 10 dbm o f p e ak po w e r ca pa b i li tie s t o th e load . n o t e th a t in cr ea sin g t h e po w e r output c a p a bi l i t i e s of t h e t x d a c re d u c e s t h e d i stor t i on p e r - fo r m a n ce d u e to t h e hig h er v o l t a g e s w i n gs s e e n a t io u t p+ and iou t p ? . s e e fi g u re 2 7 t h rou g h f i g u re 3 8 f o r p e r f or m a nc e pl ot s on t h e t x d a c s a c p e r f or m a nc e. o p t i m u m d i s t or t i on p e r f o r ma n c e can typ i cal l y b e achiev e d b y : ? li m i ti n g th e pe ak posi ti v e v io u t p + a nd v io u t p ? t o 0.8 v t o a v oi d o n s e t of t x d a c s output c o m p re ss i o n . ( t x d a c s v o l t a g e co m p l i an ce is a r o u nd 1. 2 v . ) ? limi tin g v p-p s e en a t i o utp + a n d i o utp? t o les s tha n 1.6 v . a p plica t io n s de ma ndi n g hig h er o u t p u t volt a g e swi n gs an d p o w e r dr i v e ca p a b i l i t i es can b e nef i t f r o m usin g t h e i a mp . iamp curre nt -mode oper a t ion the i a mp ca n b e co nf igur e d fo r t h e c u r r en t - m o de o p er a t io n as sh ow n i n fi g u re 6 4 f o r lo a d s rem a i n i n g re l a t i ve ly c o nst a n t . in t h is mo de, t h e pr ima r y p a t h mir r o r s sh o u ld b e u s e d t o d e liv e r t h e s i g n al- d ep e n den t c u r r en t to t h e lo ad v i a a cen t er -t a p p e d t r ans f or me r , b e c a u s e it prov i d e s t h e b e st l i ne ar it y p e r f or m a nc e . b e ca us e t h e mir r o r s exhi b i t a hi g h o u t p u t im p e dan c e , t h e y can be ea sil y ba ck -t e r m i n a t e d (i f r e q u i r ed ). f o r peak si gn al curr en t s (i o u t pk u p t o 50 ma) , o n l y th e p r ima r y p a th mir r o r ga in sh o u ld b e us ed f o r o p tim u m dis t o r t i o n p e r f o r ma n c e and p o w e r ef f i cien c y . the p r ima r y p a th s gain sh o u ld b e s e t t o 4, wi th t h e s e co nda r y p a th s ga in s t a g es s e t t o 0 ( r eg ist e r 0x10 = 0x84). th e txd a c s s t an din g c u r r en t, i, can b e s e t betw een 2. 5 ma and 12.5 ma wi th t h e iou t p o u tput s l e f t op e n . t h e iou t n output s shou l d b e co nn e c te d to t h e t r a n sfo r m e r , wi t h t h e i o u t g (a nd i o u t p)
AD9865 rev. a | page 31 of 48 output s l e f t op e n f o r opt i m u m l i n e ar it y p e r f or m a nc e. t h e tra n sf o r m e r 1 shou l d b e sp e c if ie d to hand l e t h e d c st and i ng cu rr e n t , i bi a s , dra w n b y t h e i a m p . als o , be ca us e i bi a s re m a i n s sig n al in dep e nden t, a s e r i es r e sis t o r (n o t sh o w n) ca n be in s e r t e d b e tw e e n a v dd a nd t h e t r a n sfo r m e r s ce n t er -t a p t o r e d u ce t h e i a mp s co mm on- m o d e v o l t a g e, v cm , a nd r e d u ce t h e p o w e r dissi p a t io n on t h e ic. t h e v cm b i as sh o u ld n o t exceed 5.0 v and t h e p o w e r dis s i p a t e d in t h e i a mp alo n e is as fol l o w s: p ia m p = 2 ( n + g ) i v cm ( 2 ) txdac 4493-0-022 ioutn ? ioutn+ ioutg ? ioutg+ io ut_p+ io ut_p ? 0 to ? 7.5db 0 to ? 12db iamp refio refadj r set 0.1 f r l avdd 0.1 f i bias = 2 (n+g) 1 iout pk t:1 iout pk = (n+g) 1 p_out pk = (iout pk ) 2 t 2 r l f i gure 64. cur r ent- mode o p er atio n a ste p - d ow n t r ans f or me r 1 wi th a t u r n r a tio , t , ca n be us e d t o i n c r e a s e t h e output p o w e r , p _ ou t , d e l i v e re d to t h e l o a d . th i s ca us es t h e o u t p u t lo ad , r l , to b e re f l e c te d b a ck to t h e i a m p s dif f er en t i a l o u t p u t b y t 2 , r e s u l t i n g in a la rg er di f f er en t i al v o l t a g e swi n g s e e n a t t h e i a mp s o u t p ut. f o r exa m ple , t h e i a mp can de liv e r 24 db m o f p e ak p o w e r to a 50 ? lo ad , if a 1.41:1 s t ep - do wn tra n sfo r m e r is us e d . this r e s u l t s in 5 v p-p v o l t a g e s w in gs a p p e ar i n g at io u t n + a n d io u t n ? p i ns . fi g u re 4 2 s h ow s how t h e t h ird o r der i n t e r c ept p o i n t, o i p3, o f t h e i a mp va r i es as a f u n c tion o f co mm o n -m o d e v o l t a g e o v er a 2.5 mh z t o 20.0 mh z s p a n wi t h a 2 - t o n e sig n al ha vin g a p e a k p o w e r o f a p p r o x ima t e l y 24 db m wi th i o ut pk = 50 ma. f o r a p plica t ion s r e q u ir in g an i o u t pk exce e d i n g 50 ma, s e t t h e s e co nda r y s p a t h t o de li v e r t h e addi t i o n al c u r r en t t o t h e lo ad. i o ut g+ and i o utn+ sh o u ld be sh o r t e d as we l l as i o ut g? an d io u t n ? . if iou t pk r e p r es en ts t h e p e a k c u r r en t t o b e de liv e r e d t o t h e lo ad , t h en t h e c u r r en t ga in in t h e s e conda r y pa t h , g , c a n be s e t b y th e f o ll o w i n g e q u a ti o n : g = io u t pk /12. 5 ? 4 (3) the li n e a r i t y p e r f o r ma n c e b e com e s l i mi t e d b y t h e s e conda r y m i r r or p a t h s d i stor t i on . 1 t h e b6080 and bx6090 tr ansf or mers fr om p u lse eng i neer i n g ar e w o r t h y of c o ns id era t ion f o r c u r r en t and v o l t age mod e s. iamp vol t a g e-mode oper a t ion the vol t a g e- m o de co nf igur a t ion is sh o w n i n f i gur e 65. this co nf igur a t io n is sui t e d fo r a p pli c a t io ns ha vi n g a p o o r ly def i n e d lo ad tha t ca n var y o v er a co n s idera b le ra n g e . a lo w im p e dan c e v o l t a g e dr i v er c a n b e r e ali z e d w i t h t h e addi t i o n o f tw o ext e r n al rf b i p o la r n p n tra n sis t o r s (p hil l i p s p b r951) a nd r e sis t o r s. i n t h is co nf igura t i o n, t h e c u r r en t mir r o r s in t h e pr ima r y p a t h (i o u tn o u t p u t s) fe e d in t o s c al in g r e sis t o r s, r , g e n e ra t i n g a dif f er en t i al v o l t a g e i n t o t h e b a s e s o f t h e n p n t r an sis t o r s. th es e tra n sis t o r s a r e co nf igur e d as s o ur ce fol l o w ers wi th t h e s e con - d a r y pa th cu rr en t mi rr o r s a p pea r i n g a t i o u t g+ a n d i o u t g ? p r o v id i n g a s i gnal - d epen d e n t b i a s curr e n t . n o t e th a t t h e io u t p o u tp ut s mu s t re m a i n o p e n f o r prop e r op e r a t i o n . 4493-0-023 ioutn ? ioutn+ ioutg ? ioutg+ iout_ p + iout_ p ? 0 to ? 7.5db 0 to ? 12db refio refadj r set 0.1 f to load avdd iout pk r r avdd r s 0.1 f r s 0.1 f dual npn phillips pbr951 iamp txdac f i g u re 65. v o lt ag e - m o de o p er at io n the p e ak dif f er en t i al v o l t a g e si g n al de ve lo p e d acr o s s t h e n p n s bas e s is as fol l o w s: vou t pk = r ( n i ) ( 4 ) w h er e: n is t h e ga i n s e t t in g o f t h e p r im a r y mir r o r . i is t h e s t andin g c u r r en t o f t h e txd a c def i n e d in e q ua t i on 1. the co mm o n - m o d e b i as v o l t ag e s e en a t io u t n+ and i o u t n? is a p p r o x im a t e l y a v dd ? v o u t pk , w h i l e t h e co mm on- m o d e v o l t a g e s e e n a t iout g+ and i o ut g? is a p p r o x ima t e l y t h e np n s v be dr o p b e lo w t h is le ve l ( a vd d ? v o ut pk ? 0.65). i n t h e vol t a g e - m o de co nf igur a t ion, t h e tot a l p o wer dissi p a t e d wi thin t h e i a m p is as f o l l o w s : p ia m p = 2 i {( av d d ? vou t pk ) n + ( av d d ? vou t pk ? 0.65) g} ( 5 ) the emi t t e rs o f t h e n p n t r a n sis t o r s a r e ac-co u ple d t o t h e t r a n s- fo r m er 1 via a 0. 1 f b l o c kin g c a p a ci t o r an d s e r i es r e sis t o r o f 1 ? to 2 ? . n o te t h at prote c t i on d i o d e s are no t s h ow n f o r cl ar it y p u r p os es, b u t sh o u ld b e con s ider e d if i n t e r f ac i n g t o a p o w e r o r phone l i ne. t h e a m o u n t o f s t a n di n g a n d s i gn al - d epen d e n t curr e n t used t o b i as t h e n p n tran sis t o r s de p e n d s o n t h e p e ak c u r r en t, i o ut pk , r e q u ir e d b y t h e lo ad . i f t h e lo ad is va r i a b l e , de t e r m ine t h e w o rst cas e , i o ut pk , a nd ad d 3 m a o f ma rg in to en su r e t h a t t h e n p n tra n sis t o r s r e ma in in t h e ac ti v e r e g i o n d u r i n g p e ak lo ad
AD9865 rev. a | page 32 of 48 c u r r en ts. th e g a in o f t h e s e co nda r y p a t h , g, and t h e txd a c s s t an din g c u r r en t, i, can b e s e t usin g t h e f o l l o w in g eq u a tion: io u t pk + 3 ma = g i (6) the v o l t a g e o u t p u t dr i v er exhi b i ts a hig h o u t p ut im p e dan c e if th e b i a s curr e n ts f o r th e n p n tra n si s t o r s a r e r e m o v e d . t h i s f e at u r e i s a d v a n t a g e o u s i n h a l f - d u p l e x ap p l i c at i o n s ( f o r exa m ple , p o wer lin e s) in w h ich t h e tx o u t p u t d r i v er m u st go in t o a hig h im p e dan c e s t a t e while in rx mo de . i f the AD9865 is co nf igur e d fo r t h e half-d u plex m o de (mo d e = 0), t h e i a mp , tx d a c, and i n ter p ola t io n f i l t er a r e a u to ma t i c a l l y p o w e r e d do wn a f t e r a tx b u rs t ( v ia t x e n ), th us p l ac in g th e tx dr i v er in t o a hig h i m p e dan c e s t a t e w h i l e r e d u cing i t s p o w e r co n s um p t io n. iamp curre nt c o ns um pti o n c o ns ider a t io ns the tx p a th s analog c u r r en t c o n s um p t io n is an im p o r t a n t co n s idera t io n w h e n de t e r m i n ing i t s co n t r i b u t i on t o t h e o v era l l o n -ch i p p o w e r dissi p a t io n. thi s is esp e c i a l ly t h e cas e in f u l l - d u plex a p pli c a t i o n s , w h er e t h e p o w e r dis s i p a t i o n can exce e d t h e max i m u m l i mi t o f 1.66 w , if t h e i a mp s iout pk is s e t t o hig h . the a n a l o g c u r r en t co nsum p t ion i n cl ude s t h e t x d a c s a n a l o g s u p p l y ( p i n 4 3 ) a l o n g w i th th e s t a n d i n g cu rr e n t f r o m th e i a m p s o u t p u t s. e q u a tio n 2 a nd e q u a tio n 5 ca n b e us e d t o calc u l a t e t h e p o w e r dis s i p a t e d i n t h e i a m p fo r t h e c u r r en t and v o l t a g e mo de co nf igura t io n. f i gur e 66 sh o w s t h e c u r r en t co n s um p t ion fo r t h e txd a c a n d i a mp as a f u n c t i o n o f t h e txd a c s st a n din g c u r r en t, i , w h e n on ly t h e iou t n output s are u s e d . f i g u re 6 7 show s t h e c u r r en t co n s u m p t io n fo r t h e tx d a c and i a mp as a f u n c t i o n o f t h e txd a c s s t andin g c u r r en t, i , w h en t h e i o u t n and io u t g out p ut s are u s e d . b o t h f i g u re s are w i t h t h e d e f a u l t c u r r e n t m i r r or ga in s e t t in gs o f n = 4 a n d g = 12. 04493-0-064 i (ma) i su pply (ma) 12 345 678 9 1 0 1 1 1 2 1 3 100 10 20 30 40 50 60 70 80 90 iampn output txdacs avdd f i g u re 66. cur r ent cons umpt ion of t x da c and ia m p in current -m ode o p er at ion wit h io u t n o n ly ( d ef ault i a m p s e t t i ng s ) 04493-0-065 i (ma) i su pply (ma) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 ioutn output ioutg output txdac avdd f i g u re 67. cur r ent cons umpt ion of t x da c and ia m p in current -m ode o p er at ion wit h io u t n o n ly ( d ef ault i a m p s e t t i ng s )
AD9865 rev. a | page 33 of 48 receive pa th the r e cei v e p a t h b l o c k dia g ra m f o r th e ad98 65 (o r ad9866) is s h o w n in f i gur e 68. the r e cei v e sig n al p a t h co n s is ts o f a 3-sta g e rxpga, a 3 - p o l e p r og ra mma b l e lp f , a nd a 10-b i t (o r 12-b i t) a d c . n o t e tha t th e a d d i ti o n al tw o b i t s o f r e so l u ti o n o f f e r e d b y th e ad9866 r e su l t in a 3 db t o 5 db lo w e r n o is e f l o o r dep e ndin g o n t h e rxpga ga in s e t t in g a n d lpf c u t o f f f r e q ue n c y . also w o rk in g i n co n j un cti o n w i th th e r e ce i v e pa th i s a n o f fse t c o rr e c ti o n ci r c ui t . t h ese b l ock s a r e d i scus s e d i n de ta il in t h e f o llo w in g sect i o n s . n o t e th a t th e po w e r c o n s um p t i o n o f th e r x p g a c a n be m o d i fi ed v i a reg i ster 0x 13 as dis c uss e d i n t h e p o wer c o n t r o l a nd dissi p a t ion s e c t io n. 0 to 6db ? = 1db ?6 to 18db ? = 6db ?6 to 24db ? = 6db xt a l rx ? 4 6 10 / 1 2 4493- 0- 024 register control clk syn. adc 80msps cl ko ut _ 1 cl ko ut _ 2 os c i n rx + 2 m clk multiplier 2-pole lpf 1-pole lpf spo r t p g a[ 5: 0] rx cl k r xen / syn c a d i o [1 1 : 6 ] / t x [5 :0 ] a d i o [ 1 1 :6 ]/ r x [5 :0 ] gain mapping lut spga a d 98 65 /a d 9 8 6 6 f i g u re 68. f u nc t i o n al bl ock d i ag r a m o f r x p a t h r x progr a mmable gain am plifie r the rxpga has a dig i t a l l y p r og ra mma b l e ga i n ra n g e f r o m ?12 db t o +48 db wi th 1 db r e s o l u tio n via a 6 - b i t w o rd . i t s p u r p os e is t o ext e nd t h e d y namic ra n g e o f t h e rx p a t h s u ch t h a t t h e in p u t o f t h e ad c is p r es e n te d wi t h a sig n al t h a t s c ales wi t h i n i t s f i xe d 2 v in pu t s p an. ther e a r e m u l t i p le wa ys o f s e t t in g t h e rxp g a s ga in as dis c us s e d in t h e r x pga c o n t r o l s e c t io n, as w e l l as a n a l ter n a t i v e 3-b i t ga in ma pp in g h a v i n g a ra n g e o f ?12 db t o +36 db wi t h 8 db r e s o l u tio n . t h e r x p g a i s co m p ri sed o f t w o secti o n s : a c o n t in u o u s tim e pga (cpga) fo r co urs e ga in and a s w i t ch ed c a p a ci t o r pg a (s pga) f o r f i n e ga in r e s o l u tion. the cpg a co nsis ts o f tw o cas c a d e d ga in st a g es p r o v id in g a ga in ra n g e f r o m ?12 db t o +42 db wi t h 6 db r e s o l u tio n . the f i rs t s t a g e fe a t ur es a lo w n o is e p r e a m p lif i er (< 3.0 nv/r t h z), t h er eb y e l i m ina t in g t h e n e e d fo r a n ext e r n al p r e a m p lif i er . th e sp ga p r o v ides a ga in ra n g e f r o m 0 db t o 6 db wi t h 1 db r e s o l u tion. a lo ok-u p tab l e (l ut) is us ed t o s e lec t t h e a p p r o p r i a t e gain s e t t in g f o r eac h s t a g e . the n o minal di f f er en t i al i n p u t i m p e dan c e o f t h e rxpga i n p u t a p p e a r in g a t t h e de vice r x + and r x ? in p u t p i n s is 400 ?//4 p f (20%) a nd r e ma in s r e la t i ve ly indep e n d e n t o f ga in s e t t ing. t h e p g a in p u t i s s e lf-b i a se d a t a 1 . 3 v co mm o n -m o d e lev e l all o win g maxim u m in p u t v o l t a g e swin gs o f 1.5 v a t r x + a n d r x ?. a c co u p lin g t h e in p u t sig n al t o t h is s t a g e via co u p l i n g c a p a ci t o rs (0.1 f) is r e co mmende d t o ens u r e t h a t an y ex t e r n al dc o f fs et do es n o t get am plif ie d wi t h h i g h rxpga gain s e t t in gs, p o t e n t ial l y exce e d ing t h e ad c in p u t ra n g e . t o limi t t h e rx pga s s e lf- i n d u c e d i n p u t o f fs et, a n o f fs et ca nce l la tion lo op is in c l u d e d . this can c e l la t i o n lo o p is a u t o - ma t i c a l l y p e r f o r m e d u p on p o w e r - u p a nd can a l s o b e in i t ia te d via s p i. dur i n g cal i b r a t io n, t h e rxpga s f i rs t st a g e is in t e r n al l y s h o r t e d , an d e a c h ga in s t a g e s e t t o a hig h ga in s e t t in g . a dig i t a l s e r v o l o o p s l av e s a c a l i b r at i o n d a c , w h i c h f o rc e s t h e r x i n p u t o f fs et t o b e wi t h in 32 ls b fo r t h is p a r t ic u l a r hi g h ga i n s e t t i n g. al t h o u g h t h e o f fs et va r i es fo r o t h e r ga in s e t t i n g s , t h e o f fs et is t y pi c a l l y l i mite d to 5 % of t h e a d c s 2 v i n put sp an. n o te t h a t th e o f fse t ca n c e l la ti o n ci r c ui tr y i s i n t e n d e d t o r e d u ce t h e v o l t a g e of f s e t a t t r i b ute d to on ly t h e r x p g a s i n put st age , not a n y d c o f fs ets a t t r i b ut e d t o a n exter n al s o ur ce . t h e g a i n of t h e r x p g a s h ou l d b e s e t to m i n i m i z e cl ippi ng of t h e ad c w h ile u t i l izin g m o s t of i t s d y na mic ran g e . th e maxi- m u m p e a k -t o - p e ak dif f er en t i al v o l t a g e t h a t do e s n o t r e s u l t in cl ippi ng of t h e a d c i s s h ow n i n f i g u re 6 9 . wh i l e t h e g r a p h sug g ests t h a t maxim u m i n p u t sig n a l fo r a ga in s e t t in g o f ?12 db is 8.0 v p-p , t h e maxim u m in p u t v o l t a g e in t o t h e pga sh o u l d b e l i mi te d to l e ss t h an 6 v p - p t o pre v e n t t u r n i n g on e s d pr ote c - t i on d i o d e s . fo r ap p l i c at i o n s h a v i n g h i g h e r m a x i m u m i n pu t sig n al s, con s ide r addin g an exter n al r e sist iv e a t t e n u a t or ne two r k. w h i l e t h e i n p u t s e n s i t iv i t y o f t h e rx p a t h is deg r ade d b y t h e amou n t of atte n u a t i o n on a d b - t o - d b b a s i s , t h e l o w noi s e cha r ac t e r i s t ics of t h e rxp g a p r o v i d e s o m e desig n ma rg in s u ch t h a t t h e ext e r n a l line n o is e r e ma in s t h e do minan t s o ur ce. 04493-0-031 gain (db) full-s cale p e ak-to-p e ak inp u t s p an (v ) ? 1 2 ? 6 0 6 1 2 1 82 43 0 3 64 2 4 8 8.0000 4.0000 2.0000 1.0000 0.5000 0.2500 0.1250 0.0625 0.0312 0.0156 0.0100 f i g u re 69. m a x i mu m p e ak -t o - p e ak in put v s . r x pg a g a in s e t t i ng t h at d o es not r e s u lt in a d c cl ip p i ng
AD9865 rev. a | page 34 of 48 l o w - p a ss fil t er the lo w - p a s s f i l t er (lp f ) p r o v i d es a t h ir d o r de r r e s p o n s e wi t h a c u t o ff fr e q u e n c y t h a t i s t y p i c a l l y p r o g r a m m a b l e o v e r a 1 5 m h z t o 35 mh z s p an. f i gur e 68 sh o w s tha t t h e f i rs t r e al p o le is im - p l e m e n t e d w i th i n th e fi r s t c p ga g a i n s t a g e , a n d th e c o m p l e x p o le p a ir is im pl em e n t e d i n t h e s e co nd cp ga g a in st a g e. c a p a c i t o r a r ra ys a r e us e d t o va r y t h e dif f er en t r - c t i m e con - s t a n t s wi thin t h e s e tw o s t a g e s in a m a nn e r th a t c h a n g e s th e c u t o f f f r e q uen c y w h i l e p r es er vi n g t h e n o r m ali z e d f r e q uen c y r e s p o n s e . b e c a us e a b s o l u t e r e sist o r a nd ca p a c i t o r val u es a r e p r o c es s-dep e n d en t, a cal i b r a t ion r o u t in e las t ing les s tha n 100 s a u t o ma ti call y occur s ea c h t i m e th e ta r g e t c u t o ff fr e q u e n c y r e g i s t er (reg is t e r 0x08) is u p da ted , ens u r i n g a r e p e a t a b le c u t o f f fr e q u e n c y fr o m d e v i c e t o d e v i c e . al t h o u g h t h e d e fa u l t s e t t in g sp e c if ies t h a t t h e lpf b e a c t i v e , i t ca n also be b y pa s s ed p r o v id in g a n o m i n a l f ?3 d b o f 55 mh z. t a b l e 20 sh o w s th e s p i r e g i s t ers p e r t a i nin g t o t h e l p f . tab l e 20. spi registers for rx low-pass filter a ddr ess (he x ) bit description 0x07 (0) enable rx lpf 0x08 (7:0) t a r g et va lu e t h e n o rm aliz e d w i d e ba n d ga in r e s p o n se i s s h o w n in f i gur e 70. the n o r m a l i z e d p a ss-b an d gain a nd g r o u p dela y r e sp o n s e s a r e s h o w n in f i gur e 71. the n o r m al ize d c u t o f f f r eq uen c y , f ?3 d b , r e su l t s in ?3 db a t ten u a t io n. al s o , t h e ac t u a l g r o u p dela y t i me (gd t ) r e s p o n s e ca n be calc ula t ed gi v e n a p r og ra mm e d c u t o f f f r eq uen c y usin g th e f o l l o w in g e q ua t i o n : a c t u a l gd t = n o r m a l ized gd t /(2.45 f ?3d b ) (7) 4493-0-025 frequency gain ( d b) 0 5 1.0 3.0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 2.5 2.0 1.5 0.5 f i gur e 7 0 . lp f? s no rm al iz ed wi deb a nd g a i n resp o n se 4493-0-026 normalized frequency gain ( d b) 0 0.5 1.0 0.9 0.3 0.4 0.8 0.2 0.1 normalize d group de lay tim e r e spon se ( g d t ) 1.30 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 0.25 ? 3.00 ? 2.75 ? 2.50 ? 2.25 ? 2.00 ? 1.75 ? 1.50 ? 1.25 ? 1.00 ? 0.75 ? 0.50 ? 0.25 0 0.6 0.7 normalized group delay normalized gain response f i gur e 7 1 . lp f? s no rm al iz ed p a ss -band g a in and g r o u p d e la y resp o n ses the ?3 db c u t-o f f f r eq uen c y , f ?3 d b , is p r og ra mma b l e b y wr i t ing a n 8-b i t w o r d , r e f e rr ed t o a s th e ta r g e t , t o reg i s t er 0x08. th e c u t o ff fr e q u e n c y i s a f u n c t i o n o f t h e a d c s a m p l e r a t e , f ad c , a nd t o a les s er ext e n t , t h e rxpg a ga in s e t t in g (i n db ). f i gur e 72 sho w s how t h e f r e q u e nc y re sp ons e , f ? 3 d b , va r i es as a f u n c t i o n o f th e rxpga ga in set t in g. 4493-0-027 input frequency (mhz) fundame n tal (db) 01 0 5 0 30 25 5 3 ?18 ?12 ?6 0 15 20 35 40 ?1 5 ?9 ?3 45 ? 6db gain 0db gain +6db gain +18db gain +30db gain +42db gain f i gur e 7 2 . e ffects o f rxp g a g a in on lpf f r eq uenc y response (f ?3 d b = 3 2 mh z (@ 0 db and f ad c = 80 ms p s ) the fol l o w in g fo r m u l a 1 c a n b e u s e d to e s t i ma te f ?3 d b fo r a rxpga ga in s e t t in g o f 0 db: f ?3d b _0db = (128/ ta rg et ) ( f ad c /80) ( f ad c /30 + 23.83) f (8) f i gur e 73 co m p a r es t h e m e as ure d an d calc u l a t e d f ?3 d b usin g t h is fo r m u l a. 1 em pi ri ca lly d e ri ved fo r a f ?3 d b ra n g e o f 15 mh z t o 35 mh z a n d f adc of 40 m s ps to 80 ms ps with an rxp g a = 0 d b .
AD9865 rev. a | page 35 of 48 4493-0-028 target-decimal equivalent fre q ue ncy (mhz) 48 128 224 192 96 112 176 80 64 35 15 17 19 21 23 25 27 29 31 33 144 160 208 50 msps calculated 80 msps calculated 50 msps measured 80 msps measured f i g u re 73. m e as ur e d and cal c ul at ed f ?3 db v s . t a r g et v a lu e fo r f ad c = 50 m s ps and 80 m s ps the fol l o w in g s c a l i n g fac t o r can b e a p pl ie d t o t h e p r e v io us for m u l a to c o m p e n s a te for t h e r x p g a g a i n s e tt i n g on f ?3 d b : sc a l e f a ct o r = 1 ? ( rxpga i n db )/382 (9) this s c alin g fac t o r r e d u ces t h e calc u l a t e d f ?3 d b as t h e rxpga is in cr e a s e d . a p pli c a t io ns t h a t n e e d t o ma i n t a in a mini m u m c u t- of f f r e q u e nc y , f ?3 d b _min , f o r al l r x pga ga in s e t t in gs sh o u ld f i rs t d e t e rmin e t h e s c alin g fa ct o r f o r th e h i g h e s t rxpga ga in set t in g t o be us e d . n e xt , t h e f ?3 d b _min sho u ld b e divi de d b y t h is s c a l e f a c t or to nor m a l i z e to t h e 0 d b r x p g a g a i n s e tt i n g ( f ? 3 db _0 db ). eq ua ti o n 8 ca n th en be use d t o calcula t e t h e ta r g e t v a l u e . the lp f f r e q uen c y r e s p o n s e sho w s a slig h t s e nsi t ivi t y t o te m p e r atu r e, a s sh ow n i n fi g u re 7 4 . a p pl i c a t i o n s s e ns it ive to t e m p era t ur e dr i f t ca n r e c a lib r a t e t h e lp f b y r e wr i t in g t h e t a rg et val u e t o reg i st er 0x08. 4493-0-029 target-decimal equivalent fre q ue ncy (mhz) 96 128 240 192 176 112 35 15 20 25 30 144 160 208 f out actual 80mhz and ?40 c 224 f out actual 80mhz and +25 c f out actual 80mhz and +85 c f i g u re 74. t e mpe r a t ur e d r if t of f ?3 d b for f ad c = 8 0 m s ps an d r x pg a = 0 db anal og- t o - digit a l c o nverter ( a dc ) the AD9865 f e a t ur es a 10 -b i t analog-t o-dig i t a l co n v er t e r (ad c ) ca p a b l e o f u p t o 80 ms ps. ref e r r in g t o f i gur e 68, t h e a d c i s d r i v e n b y th e s p ga s t a g e , w h i c h pe rf o r m s b o th th e s a m p le-and- h o l d an d t h e f i ne ga in a d j u st f u n c t i o n s. a b u f f er a m plif ier (n ot sh o w n) is ola t es t h e last cpga g a in st a g e f r o m t h e d y namic lo ad p r es en t e d b y t h e s p ga st a g e . the f u l l -s c a le in p u t sp a n o f t h e ad c is 2 v p - p , a nd d e p e ndi n g o n t h e pg a ga in s e t t ing, t h e f u l l -s ca le in pu t sp a n i n t o t h e s p ga is ad j u s t ab le f r o m 1 v t o 2 v in 1 db in cr em en ts. a p i p e li n e d m u l t is t a ge ad c a r chi t e c t u r e is us e d t o achi e v e h i g h s a m p le ra t e s w h i l e co n s um in g l o w p o wer . th e ad c di st r i b u t e s th e co n v ersion o v er s e v e ral smal ler a/d su bb l o c k s, r e f i nin g t h e co n v ersio n w i t h p r og r e s s i v e l y hig h er acc u rac y as i t p a s s es t h e re su l t s f r om st age to st age on e a ch cl o c k e d ge. the a d c ty p i - call y pe rf o r m s be s t w h en d r i v en in t e rn all y b y a 50% d u t y c y c l e clo c k. this is e s p e ci al l y t h e cas e w h en o p era t i n g t h e ad c a t hig h s a m p le ra te (55 ms ps t o 80 ms ps) a nd/o r lo w e r in ter n al b i as le ve ls, which ad v e rs e l y a f f e c t in t e rs t a g e s e t t lin g t i m e r e q u ir emen t s . the ad c s a m p lin g clo c k p a t h als o in cl udes a d u ty c y cle re store r c i rc u i t , w h i c h e n su re s t h a t t h e a d c ge t s a ne ar 5 0 % d u ty c y cle clo c k e v en w h en p r es en t e d wi t h a clo c k s o ur ce wi t h p o o r symm etr y (35/65). this circ ui t sh o u l d b e ena b led if t h e ad c s a m p lin g clo c k is a b u f f er e d v e rsio n o f t h e r e fer e n c e sig n al a p p e a r in g a t os cin (s e e t h e c l o c k s y n t h e si zer s e c t io n), and if t h i s re f e re nc e s i g n a l i s d e r i ve d f r om an o s c i l l a to r or cr y s t a l w h os e sp e c if ie d sy mmet r y ca nno t b e g u a r a n t e e d t o b e wi t h i n 45/55 (o r 55/45). this cir c ui t can r e ma in dis a b l ed if t h e ad c s a m p ling clo c k is der i ve d f r o m a divi de d do w n versio n o f t h e c l o c k syn t h e s i ze r s v c o , be c a us e this c l o c k is ne a r 50%. the ad c s p o wer co n s um p t io n ca n be r e d u ced b y 25 ma, wi t h mini ma l ef fe c t o n i t s p e r f o r ma n c e, b y s e t t in g bi t 4 o f reg i ster 0x07. al t e r n a t i v e p o w e r b i as s e t t in gs a r e als o a v a i la b l e v i a reg i ster 0x 13, as dis c uss e d i n t h e p o w e r c o n t r o l a n d d i ss i p a t ion s e c t ion. l a st ly , t h e a d c c a n b e c o m p l e tely p o we re d do wn f o r half-d u p lex o p era t io n, f u r t h e r r e d u cin g t h e AD9865 s peak po w e r c o n s u m p t i o n .
AD9865 rev. a | page 36 of 48 04493-0-066 1.0v to adcs reft refb c1 0.1 f c2 10 f c3 0.1 f c4 0.1 f c1 c4 c2 c3 top view f i gure 7 5 . adc ref e r e nc e a n d d e c o up l i n g t h e a d c h a s a n i n te r n a l vo lt a g e re f e re nc e a n d re f e re nc e a m p l i - f i er as s h o w n in f i gur e 75. th e in t e r n al ban d g a p r e f e r e n c e ge ne r a te s a s t ab l e 1 v re fe re nc e l e vel t h a t i s c o n v e r te d to a di f - f e re n t i a l 1 v re f e re nc e c e n t e r e d ab out m i d - sup p l y ( a v d d / 2 ) . the o u t p u t s o f t h e dif f er en t i al refer e n c e am plif i e r a r e a v a i la b l e a t t h e ref t and ref b p i ns a nd mu s t b e p r o p e r ly de co u p le d fo r opt i m u m p e r f or m a nc e. t h e r e f t an d r e f b pi ns are c o n v e n - ien t l y si t u a t e d a t t h e co r n ers o f t h e cs p p a cka g e s u ch t h a t c1 (0603 typ e ) can be p l aced dir e c t l y acr o s s i t s p i n s . c3 a nd c4 ca n b e pl ace d u nder n e a t h c1, an d c 2 (10 f t a n t a l u m ) can b e place d f u r t h e st f r o m t h e p a ck age. table 21. spi r e gisters for rx adc a ddr ess he x bit description 0x04 (5) dut y c y cle r e stor e cir c uit (4) adc clock fr om pll 0x 07 (4) adc l o w pow er mode 0x13 (2:0) adc po w e r bi as adjust a g c tim i ng c o nsider a t io ns w h e n im p l e m en ti n g a d i gi tal a g c ti mi n g loo p , i t i s im po r t a n t t o co n s ider t h e rx p a th l a t e n c y a nd s e t t l i n g t i me o f th e rx p a th in r e s p o n s e t o a c h a n g e in ga in s e t t ing. f i gur e 2 1 a nd f i gur e 24 sho w t h e rx pg a s s e t t l i n g r e sp o n s e to a 60 db a nd 5 db chan ge in ga i n s e t t in g w h en usin g t h e tx[ 5 :0] o r pga[ 5:0] p o r t . w h i l e t h e rx pga s e tt l i n g t i me ma y a l s o sho w a sli g h t dep e nde n c y o n th e l p f s cu t- o f f f r eq ue n c y , th e a d c s p i pe lin e d e la y alo n g wi t h t h e ad i o b u s i n t e r f ac e p r es en t s a m o r e sig n if i c a n t del a y . th e amou n t of d e l a y or l a te nc y i s d e p e n d e n t on w h e t he r a h a l f - or f u l l -d u p lex is s e le c t e d . an im p u ls e r e s p o n s e a t t h e rxp g a s in p u t can be obs e r v ed a f t e r 10. 0 ad c c l o c k c y c l es (1/f ad c ) in th e cas e o f a hal f -d u p lex in t e r f ace , an d 10.5 ad c c l o c k c y c l es in t h e cas e o f a f u l l -d u p lex i n t e r f ac e. this la te n c y , a l o n g w i t h t h e r x p g a set t li n g tim e , s h o u ld be c o n s i d e r ed t o e n s u r e s t a b ili t y o f th e a g c loo p .
AD9865 rev. a | page 37 of 48 clock synthesizer the AD9865 g e n e ra t e s al l i t s in t e r n al s a m p l i n g c l o c ks, as we l l as tw o us er -p r o g r a mma b l e clo c k ou t p uts a p p e a r ing a t cl k o u t 1 an d c l k o u t 2 , f r om a s i ng l e re f e re nc e so u r ce as s h o w n i n f i g u re 7 6 . t h e r e f e re nc e s o ur ce ca n b e e i t h er a f u ndam e n t a l f r eq ue n c y o r a n o v e r t o n e q u a r tz cr ys tal co n n ec t e d bet w een oscin and x t al w i t h t h e p a r a l l el r e s o na n t lo ad co m p on en ts as sp e c if ie d b y t h e cr y s t a l man u fac t ur er . i t can a l s o b e a t t l- le vel clo c k a p pl i e d to osci n wi t h x t al lef t u n co nn e c te d. the da t a r a te, f da t a , fo r t h e tx a nd rx da t a p a t h s m u st a l wa y s b e e q ual . th er efo r e , t h e ad c s s a m p le ra te , f ad c , is al wa ys e q ual to f da t a w h i l e t h e t x d a c up d a te r a te i s a f a c t or of 1 , 2 , or 4 of f da t a , de p e n d ing o n t h e i n ter p o l a t ion fac t o r s e l e c t e d . t h e da t a ra t e r e f e rs t o the w o r d ra t e and s h o u l d n o t be c o nf us ed wi t h t h e n i b b l e ra t e in fu ll- d u p le x in t e rface . 2 n xt a l c1 2 l 2 r 2 m clk multiplier c2 xt a l os c i n cl ko ut 2 cl ko ut 1 to a d c to tx d a c 04493- 0- 030 f i gure 76. cl ock o s cil l a to r and s y nthe s i z e r the 2 m clk m u l t i p lier co n t a i ns a p ll ( w i t h in te g r a t e d lo o p f i lte r ) and v c o c a p a bl e of ge ne r a t i ng a n output f r e q u e nc y t h a t is a m u l t i p le o f 1, 2, 4, o r 8 o f i t s in p u t r e f e r e n c e f r eq uen c y , f osci n , ap p e a r i n g at o s c i n . t h e i n p u t f r e q u e n c y r a n g e o f f osci n is betw een 20 mh z and 80 m h z, while t h e v c o can o p era t e o v er a 40 mh z to 200 mh z s p an. f o r th e best p h as e n o is e/ji t t e r cha r ac t e r i s t ics, i t is advis a b l e t o o p era t e t h e v c o w i t h a f r e - q u en c y b e tw een 100 mh z and 2 00 mh z. th e v c o o u t p u t dr i v es t h e txd a c dir e c t l y s u ch tha t i t s u p da t e ra t e , f dac , is rel a te d to f osci n b y th e f o ll o w i n g e q u a ti o n : f da c = 2 m f oscin (10) w h er e m = 0, 1, 2, o r 3. m is th e p l l s m u l t i p lica t i o n f a c t o r s e t in reg i s t er 0x04. th e val u e o f m is det e r m in e d b y t h e tx p a th s w o r d ra t e , f da t a , a nd dig i t a l i n ter p ol a t io n fac t o r , f , as sho w n i n t h e fol l o w i n g eq ua ti o n : m = log 2 ( f f da t a /f oscin ) ( 1 1 ) n o te : i f t h e re f e re nc e f r e q u e nc y a p p e ar i n g at o s c i n i s c h o s e n t o be e q ual t o t h e AD9865 s tx a nd rx p a t h s wo r d ra t e , t h en m is sim p l y e q u a l to log 2 (f). the c l o c k s o ur ce f o r th e ad c c a n b e s e lec t e d in reg i s t er 0x04 as a b u f f er e d v e rsio n o f t h e r e fe r e n c e f r e q ue n c y a p p e a r i n g a t oscin (d efa u l t s e t t in g) o r a divid e d version o f t h e v c o ou t p ut (f da c ). t h e f i rst o p t i o n is t h e def a u l t s e t t in g and m o st desir a b l e if f osci n is e q u a l t o th e ad c s a m p le ra te , f ad c . this o p t i on typ i c a l l y r e s u l t s in t h e b e st ji t t e r / phas e n o is e p e r f o r ma n c e fo r th e a d c sa m p li n g c l oc k. th e s e c o n d o p ti o n i s s u i t a b l e in c a se s w h er e f osci n i s a f a c t or of 2 or 4 le ss t h an t h e f ad c . i n t h is cas e , t h e divi der r a t i o , n, is ch o s en such t h a t t h e divi de d d o wn v c o o u t p u t is eq u a l to th e ad c s a m p le ra t e , as sho w n in t h e fol l o w ing e q u a t i o n : f ad c = f da c / 2 n (12) w h er e n = 0, 1, o r 2. f i gur e 77 sh o w s t h e deg r ada t ion i n phas e n o is e p e r f o r ma n c e im p a r t e d on t o t h e ad c s s a m p l i n g clo c k fo r dif f er en t v c o o u t p u t f r eq uen c ies. i n this cas e , a 25 mh z, 1 v p-p sine wa v e was us e d to dr i v e oscin , an d t h e pll s m an d n fac t o r s w e r e s e lec t e d t o p r o v ide an f ad c of 5 0 m h z f o r v c o op e r a t i n g f r eq uen c ies o f 50, 100, a nd 200 mh z. th e rxp g a in p u t was dr i v en w i t h a ne a r f u l l -s ca le, 1 2 .5 mh z in pu t s i g n a l wi t h a gai n s e t t in g o f 0 db . o p era t i n g t h e v c o a t t h e hig h es t p o s s ib le f r e q uen c y r e su l t s in t h e b e st na r r o w a nd wide b a nd phas e n o is e ch ar a c te r i st i c s . f o r c o m p ar i s on pu r p o s e s , t h e c l o c k s o u r c e for th e a d c w a s ta k e n di r e ctl y f r o m o s c i n w h en d r i v e n b y a 50 mh z s q ua r e wa v e . 04493-0-067 frequency (mhz) dbfs 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 0 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 direct vco = 50mhz vco = 100mhz vco = 200mhz f i g u re 77. co mp ari s on of p h as e no is e p e r f o r m a nce wh en a d c cl ock s o u r c e i s d e ri v e d fro m di ff er ent vc o o u tput f r equ e nci e s the cl k syn t hesizer als o has tw o c l o c k o u t p u t s a p p e a r in g a t clk o ut1 and clk o ut2. th e y a r e p r og ra mm a b le v i a reg i st er 0x06. b o th o u t p u t s ca n be in v e r t ed o r dis a b l ed . th e volt age l e v e l s a p p e ar i n g a t t h e s e out p ut s are rel a t i ve to dr v d d an d re m a i n a c t i ve d u r i n g a h a r d w a re or s o f t w a re re s e t . t a bl e 2 2 s h o w s t h e sp i r e g i s t ers p e r t a i ni n g t o t h e clo c k s y n t h e si zer . clk o ut1 is a divide d versio n o f t h e v c o o u tp u t an d ca n b e s e t to b e a su b m u l t i pl e i n te ge r of f da c (f dac /2 r , w h er e r = 0, 1, 2, or 3 ) . b e c a u s e t h i s cl o c k i s a c tu a l ly d e r i ve d f r om t h e s a me s e t of d i v i de r s used w i th i n t h e p l l co r e , i t i s p h a s e- l o c k ed t o t h em s u c h tha t i t s p h a s e r e la ti o n s h i p r e la t i v e t o t h e sign al a p p e a r i n g
AD9865 rev. a | page 38 of 48 at oscin (or rxclk) can be determined upon power up. also, this clock has near 50% duty cycle, because it is derived from the vco. as a result, clkout1 should be selected before clkout2 as the primary source for system clock distribution. clkout2 is a divided version of the reference frequency, f oscin , and can be set to be a submultiple integer of f oscin (f oscin /2 l , where l = 0, 1, or 2). with l set to 0, the output of clkout2 is a delayed version of the signal appearing at oscin, exhibiting the same duty cycle characteristics. with l set to 1 or 2, the output of clkout2 is a divided version of the oscin signal, exhibiting a near 50% duty cycle, but without having a determi- nistic phase relationship relative to clkout1 (or rxclk). table 22. spi registers for clk synthesizer address (hex) bit description 0x04 (4) adc clk from pll (3:2) pll divide factor (p) (1:0) pll multiplication factor (m) 0x06 (7:6) clkout2 divide number (5) clkout2 invert (4) clkout2 disable (3:2) clkout1 divide number (1) clkout1 invert (0) clkout1 disable
AD9865 rev. a | page 39 of 48 power control and dissipation power-down the AD9865 provides the ability to control the power-on state of various functional blocks. the state of the pwrdwn pin along with the contents of register 0x01 and register 0x02 allow two user-defined power settings that are pin selectable. the default settings 1 are such that register 0x01 has all blocks powered on (all bits 0), while register 0x02 has all blocks powered down excluding the pll such that the clock signal remains available at clkout1 and clkout2. when the pwrdwn pin is low, the functional blocks corresponding to the bits in register 0x01 are powered down. when the pwrdwn is high, the functional blocks corresponding to the bits in register 0x02 are powered down. pwrdwn immediately affects the designated functional blocks with minimum digital delay. table 23. spi registers associated with power-down and half-duplex power savings address (hex) bit description comments 0x01 (7) pll (6) txdac/iamp (5) tx digital (4) ref (3) adc cml (2) adc (1) pga bias (0) rxpga pwrdwn = 0. default setting is all functional blocks powered on. 0x02 (7) pll (6) txdac/iamp (5) tx digital (4) ref (3) adc cml (2) adc (1) pga bias (0) rxpga pwrdwn = 1. default setting is all functional blocks powered off excluding pll. 0x03 (7:3) tx off delay (2) rx pwrdwn via txen (1) enable tx pwrdwn (0) enable rx pwrdwn half-duplex power savings. 1 with mode = 1 and config =1, reg. 0x02 default settings are with all blocks powered off, with rxclk providing a buffered version of the signal appearing at oscin. this setting results in the lowest power consumption upon power-up, while stil l allowing AD9865 to generate the system clock via a crystal. half-duplex power savings significant power savings can be realized in applications having a half-duplex protocol allowing only the rx or tx path to be operational at any instance. the power savings method depends on whether the AD9865 is configured for a full- or half-duplex interface. functional blocks having fast power on/off times for the tx and rx path are controlled by the following bits: txdac/iamp, tx digital, adc, and rxpga. in the case of a full-duplex digital interface (mode = 1), one can set register 0x01 to 0x60 and register 0x02 to register 0x05 (or vice versa) such that the AD9865s tx and rx path are never powered on simultaneously. the pwrdwn pin can then be used to control which path is powered on, depending on the burst type. during a tx burst, the rx paths pga and adc blocks can typically be powered down within 100 ns, while the tx paths dac, iamp, and digital filter blocks are powered up within 0.5 s. for an rx burst, the tx paths can be powered down within 100 ns, while the rx circuitry is powered up within 2 s. setting the txquiet pin low allows it to be used with the full- duplex interface to quickly power down the iamp and disable the interpolation filter. this is meant to maintain backward compatibility with the ad9875/ad9876 mxfes with the excep- tion that the txdac remains powered, if its ioutp outputs are used. in most applications, the interpolation filter needs to be flushed with 0s before or after being powered down. this ensures that upon power-up, the txdac (and iamp) have a negligible differential dc offset, thus preventing spectral splatter due to an impulse transient. applications using a half-duplex interface (mode = 0) can benefit from an additional power savings feature made available in register 0x03. this register is effective only for a half-duplex interface. besides providing power savings for half-duplex applications, this feature allows the AD9865 to be used in applications that need only its rx (or tx) path functionality through pin-strapping, making a serial port interface (spi) optional. this feature also allows the pwrdwn pin to retain its default function as a master power control, as defined in table 10. the default settings for register 0x03 provide fast power control of the functional blocks in the tx and rx signal paths (outlined above) using the txen pin. the txdac still remains powered on in this mode, while the iamp is powered down. significant current savings are typically realized when the iamp is powered down. for a tx burst, the falling edge of txen is used to generate an internal delayed signal for powering down the tx circuitry. upon receipt of this signal, power-down of the tx circuitry
AD9865 rev. a | page 40 of 48 o c c u rs w i t h in 1 00 n s . th e us er - p r o g r a mma b l e dela y fo r t h e tx p a t h p o w e r - do w n is me a n t to ma tch t h e pi p e li n e dela y o f t h e las t tx b u rst s a m p le s u c h tha t p o w e r - do wn o f th e txd a c an d i a mp do es n o t im p a c t i t s t r a n smis sio n . a 5 - b i t f i e l d in r e g i s t er 0x0 3 s e ts t h e del a y f r o m 0 t o 31 t x clk c l o c k c y c l es, wi th t h e def a u l t bein g 31 (0. 62 s wi th f tx c l k = 50 ms ps). th e dig i t a l in ter p ola t i o n f i l t er is a u t o ma t i cal l y f l us h e d wi th mids c a le s a m p les p r io r t o p o w e r - do wn, if t h e clo c k sig n a l in t o t h e t x cl k p i n is p r es en t for 3 3 addi t i ona l cl o c k c y cl es af ter t x e n r e t u r n s lo w . f o r a n rx b u rs t, the r i sin g edg e o f t x en is us ed t o g e n e ra t e a n in t e r n al si gn al (w i t h n o d e la y) th a t po w e r s u p th e t x ci r c ui tr y w i th i n 0. 5 s . the rx p a t h p o w e r - o n / p o w er - o f f ca n b e con t rol l e d b y ei t h er t x e n o r r x e n b y s e t t in g bi t 2 o f reg i s t er 0x 03. i n t h e def a u l t s e t t ing, t h e f a l l in g edg e o f t x e n p o w e rs u p t h e rx cir c ui tr y wi thin 2 s, whi l e the r i sin g edge o f t x e n p o wers do wn t h e rx cir c ui tr y wi t h in 0.5 s. i f r x e n is s e lec t e d as t h e co n t r o l sig n al , th en i t s r i sin g e d g e p o wers u p t h e rx c i r c ui tr y a nd t h e fal l i n g e d ge p o w e rs i t do wn. t o dis a b l e t h e fast p o w e r - do w n o f t h e tx a nd/o r rx cir c u i t r y , s e t bi t 1 and/o r bi t 0 to 0. po wer reduc t ion options the p o wer co n s um p t ion o f the AD9865 can be sig n if ican tl y r e d u ce d f r o m i t s defa u l t s e t t i n g b y o p t i miz i n g t h e p o w e r c o nsu m pt i o n ve r s u s p e r f or m a nc e of t h e v a r i ou s f u nc t i on a l b l o c ks in t h e tx a nd rx sig n al p a th. o n t h e tx p a th, minim u m p o w e r co n s u m pt io n is r e a l i z e d w h en t h e tx d a c o u t p ut is us e d dir e c t ly an d i t s st an d i n g c u r r en t, i, is r e d u ce d to as lo w as 1 m a . a l t h ou g h a sl i g h t d e g r a d a t ion i n t h d p e r f or manc e re su lts a t r e d u ce d st an d i ng c u r r en ts, i t o f ten r e ma i n s ade q ua te fo r m o st ap p l i c at i o n s , b e c a u s e t h e o p a m p d r i v e r t y p i c a l l y l i m i t s t h e o v eral l lin e a r i t y p e r f o r ma n c e o f th e tx p a t h . the lo ad r e sis t o r s us e d a t t h e tx d a c o u t p uts (i ou tp+ a nd iou t p?) ca n b e i n c r e a s e d to ge ne r a te a n a d e q u a te di f f e r e n t i a l v o lt age t h a t c a n b e f u r t her a m pl if ie d vi a a p o w e r ef f i cien t o p -am p -b a s e d dr i v e r s o lut i on . fi g u re 7 8 show s ho w t h e s u pply c u r r e n t f o r t h e txd a c (p in 43 ) is r e d u ced f r o m 55 ma t o 14 ma as t h e s t an din g c u r r en t is r e d u ced f r o m 12.5ma t o 1. 25 ma. f u r t h e r t x po w e r s a vi n g s ca n be a c h i ev ed b y b y pa s s i n g o r r e d u ci n g t h e i n te r p o l a t i o n f a c t or of t h e d i g i t a l f i lte r a s s h ow n i n f i g u re 7 9 . 04493-0-068 i standing (ma) iavdd txdac (ma) 01 23 45 67 89 1 0 1 1 1 2 1 3 55 10 15 20 25 30 35 40 45 50 f i gure 78. reduc t ion in t x d a c s sup p l y c u rrent vs. stand i ng c u r r ent 04493-0-069 input data rate (msps) i dv dd (ma) 20 30 40 50 60 70 80 55 60 65 15 20 25 30 35 40 45 50 2 interpolation 4 interpolation 1 (half-duplex only) f i gure 79. d i g i tal s u p p ly c u rrent c o nsumption vs. input d a t a rate (dvdd = dr vdd = 3 .3 v and f ou t = f da t a /1 0) p o w e r co n s u m p t io n o n t h e rx p a th ca n be ac hie v ed b y r e d u c- in g t h e b i as le vels o f t h e va r i o u s a m plif iers co n t a i ne d w i t h i n t h e rxpga an d ad c. a s p r e v i o u s l y n o t e d , t h e rx pga co n s is ts o f tw o cpg a a m plif iers a nd on e spga a m pl if ier . the b i as l e v e l s of e a ch of t h e s e am pl i f i e r s a l ong w i t h t h e a d c c a n b e c o n - tr ol led via reg i st er 0x13, as s h o w n in t a b l e 24. the def a u l t s e t t in g f o r 0x13 is 0x00. table 24. spi r e gister for rxp g a and adc b i asing a ddr ess (he x ) bit description 0x07 (4) adc lo w pow er 0x13 (7:5) cpga bias adjust (4:3) spga bias adj u st (2:0) adc po w e r bias adj u s t
AD9865 rev. a | page 41 of 48 b e ca us e t h e cp ga p r o c es s e s si g n als in t h e con t in uo us t i m e do ma i n , i t s p e r f o r ma n c e vs. b i a s s e t t in g r e mains m o st ly inde p e n d e n t o f t h e s a m p le ra t e . t a b l e 25 sh o w s h o w t h e typ i cal c u r r en t co n s u m p t io n s e en a t a v d d (p in s 35 and 40) va r i es as a f u n c t i on o f bi ts (7:5), w h i l e t h e r e ma ini n g b i ts ar e ma in t a i n e d a t th eir def a u l t s e t t in gs o f 0. onl y f o ur o f th e p o s s ib le s e t t in gs r e su l t in an y r e d u c t io n i n c u r r en t co n s um p t io n r e la t i v e t o t h e defa u l t s e t t i n g. re d u cin g t h e b i as le v e l typ i c a l l y r e su l t s in a deg r a d a t io n i n t h e thd vs. f r e q uen c y p e r f o r ma n c e as sh o w n in f i gur e 80. this is d u e t o a r e d u c t io n o f t h e am plif ier s uni t y ga in ba n d w id th, wh i l e th e s n r pe rf o r m a n c e r e m a in s r e la ti v e l y una f f e c t ed . table 25. a n alog suppl y curr en t v s . cpga b i as settin g s at f adc = 65 msps bit 7 bit 6 bit 5 ? ma 0 0 0 0 0 0 1 ? 2 7 0 1 0 ? 4 2 0 1 1 ? 5 1 1 0 0 ? 5 5 1 0 1 2 7 1 1 0 6 9 1 1 1 2 7 04493-0-091 cpga bias setting-bits (7:5) s nr (dbfs ) thd (dbc ) 000 100 010 011 001 65.0 40.0 ?20 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 snr_rxpga = 0db snr_rxpga = 36db thd_rxpga = 0db thd_rxpga = 36db f i g u re 80. th d v s . f in p e r f or m a nce a n d r x pg a bias s e t t i ng s (0 00 ,001 ,01 0 ,10 0 wi th rxp g a = 0 a n d + 3 6 db a n d ain = ? 1 dbfs, lp f set to 2 6 mh z, a n d f ad c = 50 msp s ) the s p g a is i m plem e n t e d as a swi t ch e d ca p a c i t o r a m plif ier ; t h er efo r e , i t s p e r f o r ma n c e vs. b i as le v e l is m o s t ly dep e n d e n t on t h e s a m p le ra t e . f i gur e 81 sh o w s h o w t h e typ i ca l c u r r en t co n s um p t io n s e en a t a v dd (pi n 35 an d pi n 40 ) va r i es as a f u n c tio n o f b i ts (4:3) a n d sam p le ra t e , w h i l e t h e r e ma ining b i ts a r e ma in ta in e d a t t h e defa u l t s e t t in g o f 0. f i gure 82 sh o w s h o w t h e s n r and t h d p e r f o r ma n c e is a f fe c t e d fo r a 10 mhz si n e wa v e in p u t as t h e ad c s a m p le r a t e is sw e p t f r o m 20 mhz t o 8 0 mh z . th e s n r a n d thd per f o r m a n c e r e m a i n s r e la t i v e l y s t a b le, sug g est i n g t h a t t h e s p ga b i as c a n o f ten b e r e d u ce d f r o m i t s de - fa u l t s e t t in g w i t h o u t im p a c t in g t h e de vi ce s o v er a l l p e r f o r ma n c e. 04493-0-070 adc sample rate (msps) i av dd (ma) 20 30 40 50 60 70 80 210 170 175 180 185 190 195 200 205 01 00 10 11 f i gure 8 1 . a v dd c u rr ent vs . sp g a bia s setti ng a n d sam p le r a t e 04493-0-092 sample rate (msps) s nr (dbc ) thd (dbc ) 20 80 60 70 30 40 50 61 51 ?54 ?74 ?72 ?70 ?68 ?66 ?64 ?62 ?60 ?58 ?56 52 53 54 55 56 57 58 59 60 snr-00 snr-01 snr-10 snr-11 thd-00 thd-01 thd-10 thd-11 f i g u re 82. snr and thd p e r f o r man c e v s . f ad c a n d sp g a bia s setting wi th rxp g a = 0 db , f in = 10 m h z, lpf s e t to 26 m h z, and a i n = ?1 d b fs t h e a d c i s ba s e d o n a p i p e lin e a r c h i t ec t u r e w i th ea ch s t a g e co n s ist i n g o f a s w i t ch e d ca p a c i to r a m plif ier . t h er efo r e , i t s p e r - f o r m a n ce vs. b i as le v e l is m o s t ly dep e n d e n t on th e s a m p le ra t e . f i gur e 83 sh o w s h o w t h e typ i cal c u r r en t co n s u m p t ion s een a t a v d d (p in s 35 a nd 40) va r i es as a f u n c tio n o f b i ts (2:0) a nd s a m p le ra te , w h ile t h e r e ma ining b i ts a r e ma i n t a ine d a t t h e defa u l t s e t t in g of 0. s e t t in g b i t 4 o r reg i s t er 0x0 7 co r r es p o n d s t o th e 011 s e t t ing, an d t h e s e t t ings o f 101 a n d 11 1 r e s u l t in hig h er c u r r en t c o n s um pt io n. f i gur e 84 s h o w s ho w t h e snr and thd p e r f o r ma n c e a r e a f fe c t e d fo r a 10 mh z si n e wa ve i n p u t f o r th e lo w e r p o w e r set t in gs as t h e ad c sam p le ra t e is sw ep t f r o m 20 mh z to 80 mh z.
AD9865 rev. a | page 42 of 48 04493-0-071 sample rate (msps) i av dd (ma) 20 30 40 50 60 70 80 220 120 130 140 150 160 170 180 190 200 210 000 001 010 011 100 101 101 or 111 f i gure 8 3 . a v dd c u rr ent vs . adc bia s s e tti ng a n d s a m p l e r a t e 04493-0-092 sample rate (msps) s nr (dbc ) thd (dbc ) 20 80 60 70 30 40 50 61 51 ?54 ?74 ?72 ?70 ?68 ?66 ?64 ?62 ?60 ?58 ?56 52 53 54 55 56 57 58 59 60 thd-000 thd-001 thd-010 thd-011 thd-100 thd-101 snr-000 snr-001 snr-010 snr-011 snr-100 snr-101 f i g u re 84. snr and thd p e r f o r man c e v s . f ad c a n d adc bia s setting wi th rxp g a = 0 db , f in = 10 m h z, and a i n = ?1 d b fs a si n e w a v e in pu t is a st and a r d a nd con v enie n t m e t h o d o f a n al yzin g t h e p e r f o r ma n c e o f a sys t em. h o w e ver , t h e am o u n t o f p o w e r r e d u c t ion t h a t is p o ssib l e is a p pli c a t ion dep e nden t , b a s e d o n t h e na t u r e o f th e in p u t wa v e fo r m (s uc h as f r eq uen c y co n t en t, p e a k - to -r m s r a t i o ) , t h e min i m u m ad c s a m p le, a nd t h e m i ni - m u m ac c e pt abl e l e vel of p e r f or manc e. t h u s , i t i s adv i s a bl e t h a t p o w e r - s e n s i t i v e a p plic a t io n s opt i mi ze t h e p o we r b i as s e t t in g o f th e r x pa th usin g a n in p u t wa v e f o rm th a t i s r e p r e s e n t a ti v e o f t h e ap p l i c at i o n . po wer diss ip a t ion the p o wer dis s i p a t io n o f t h e AD9865 ca n becom e q u i t e hig h in f u l l -d u p lex a p pl ica t io n s i n w h ich t h e tx a nd rx p a t h s a r e si- m u l t an e o usly op er a t i n g wi t h no mina l p o w e r b i as s e t t in gs. i n fac t , s o m e a p pli c a t io ns t h a t us e t h e i a mp ma y n e e d t o ei t h er r e d u c e i t s peak po w e r ca pa b i li tie s o r r e d u c e th e po w e r c o n - s u m p t i o n o f t h e r x pa th , so tha t th e devi ce s ma xi m u m allo w a b l e po w e r co n s um p t i o n , p max , i s n o t e x ceed ed . p max is sp e c if ie d a t 1.66 w t o e n sur e t h a t t h e d i e t e m p era t ur e do es n o t exceed 125 o c at a n a m b i e n t t e mp e r at u r e o f 8 5 o c. this sp e c if ic a t ion is b a s e d on t h e 64 -p in lfscp ha v i n g a t h er ma l re s i st anc e , ja , o f 24 o c / w w i t h it s he a t slu g s o l d e r e d . ( t he ja is 30.8 o c/w , if t h e h e a t s l u g r e ma in s un s o lder e d .) i f a p a r t ic u l a r ap p l i c at i o n s m a x i mu m a m b i e n t t e mp e r a t u r e , t a , fal l s b e lo w 85 o c, t h e max i m u m a l lo wab l e p o w e r diss i p a t i o n can b e de ter - mi n e d b y t h e fol l o w i n g e q ua t i on: p ma x = 1.66 + (8 5 ? t a )/24 (13) a s sumi n g t h e i a mp s co mm on-mo d e b i as v o l t a g e is o p er a t in g o f f th e s a m e a n alog s u p p l y as th e AD9865, t h e f o l l o w in g eq ua - t i o n can b e us e d t o calc u l a t e t h e maxim u m t o t a l c u r r en t co n s um p t io n, i max , o f t h e i c : i ma x = ( p ma x ? p ia m p )/3.47 (14) w i t h an am b i en t t e m p era t ur e o f u p t o 85c, i max is 478 ma. i f t h e i a mp is op era t in g o f f a dif f er en t s u p p l y o r in t h e v o l t a g e m o de co nf igur a t io n, f i rst c a lc u l a t e t h e p o w e r di ssi p a t e d i n t h e ia m p , p ia m p , usin g e q ua tio n 2 or e q ua tion 5, and t h en re c a l c u l ate i max , usin g e q ua t i o n 14. f i gur e 78, f i gure 79, f i gur e 81, a nd f i gur e 83 c a n b e us ed t o calc u l a t e t h e c u r r en t co n s u m p t io n o f t h e rx a nd tx p a t h s fo r a gi v e n s e t t i n g . mode sele c t upon power-up and rese t the AD9865 p o w e r - u p s t a t e is det e r m in ed b y t h e log i c leve ls a p p e ar i n g a t t h e mode and c o n f ig pi ns . t h e mode pi n i s us e d t o s e le c t a half- o r f u l l -d u p lex in t e r f ac e b y p i n s t r a p p i n g i t l o w or hig h , re sp e c t i v e ly . t h e c o nf i g p i n is u s e d i n c o n j u n c - t i o n w i th th e m o d e p i n t o d e t e rm i n e th e d e f a ul t s e t t i n g s f o r t h e s p i r e g i s t ers as o u t l i n e d i n t a b l e 10. the i n t e n t o f t h es e p a r t ic u l a r defa u l t s e t t in gs is t o al lo w s o m e a p plic a t io n s t o a v o i d using t h e s p i (dis a b le d b y p i n- st ra p p in g se n h i gh ), t h e r eb y r e d u ci n g im p l e m en ta ti o n cos t s. f o r ex a m ple, s e t t in g mode lo w a nd c o nf i g hig h co nf igur es t h e AD9865 t o be b a c k wa rd co m p a t i b le wi t h t h e ad9975, whil e s e t t in g mode hig h and c o nf i g lo w ma k e s i t b a ckwa r d co m p a t i b le wi th th e ad9875. o t h e r a p p l ic a t io ns m u s t us e t h e s p i to co nf igur e t h e de vic e . a h a rdw a re ( res e t pi n ) or s o f t w a re ( b i t 5 o f reg i s t er 0x00) r e s e t can b e us e d t o p l ac e t h e AD9865 in t o a k n o w n s t a t e o f o p era t io n as de ter m i n e d b y t h e s t a t e o f t h e mo d e a n d c o nf i g p i n s . a dc o f fs et ca l i b r a t io n and f i l t er t u ni n g r o u t i n e is a l s o ini t i a t e d u p o n a h a r d wa re r e s e t, b u t n o t wi t h a s o f t wa r e re s e t . n e it he r re s e t me t h o d f l u s he s t h e d i g i t a l i n te r p o l at i o n f i l t ers in t h e tx p a t h . refer t o t h e h a lf-d u p lex m o de an d f u l l - d u plex m o de s e c t io n s fo r info rma t io n on f l ush i n g t h e dig i t a l fi l t e r s . a h a rdw a re r e s e t can b e t r ig gere d b y p u lsin g t h e res e t pi n l o w fo r a mini m u m o f 50 n s . the s p i r e g i s t ers a r e ins t a n t l y r e s e t t o th ei r d e fa ul t s e t t i n gs u p o n res e t g o in g lo w , w h il e t h e dc o f fs et
AD9865 rev. a | page 43 of 48 calibration and filter tuning routine is initiated upon reset returning high. to ensure sufficient power-on time of the various functional blocks, reset returning high should occur no less than 10 ms upon power-up. if a digital reset signal from a microprocessor reset circuit (such as adm1818) is not available, a simple r-c network referenced to dvdd can be used to hold reset low for approximately 10 ms upon power- up. analog and digital loop-back test modes the AD9865 features analog and digital loop-back capabilities that can assist in system debug and final test. analog loop-back routes the digital output of the adc back into the tx data path prior to the interpolation filters such that the rx input signal can be monitored at the output of the txdac or iamp. as a result, the analog loop-back feature can be used for a half- or full-duplex interface, to allow testing of the functionality of the entire ic (excluding the digital data interface). for example, the user can configure the AD9865 with similar settings as the target system, inject an input signal (sinusoidal waveform) into the rx input, and monitor the quality of the reconstructed output from the txdac or iamp to ensure a minimum level of performance. in this test, the user can exercise the rxpga as well as validate the attenuation char- acteristics of the rxlpf. note that the rxpga gain setting should be selected such that the input does not result in clipping of the adc. digital loop-back can be used to test the full-duplex digital interface of the AD9865. in this test, data appearing on the tx[5:0] port is routed back to the rx[5:0] port, thereby confirming proper bus operation. the rx port can also be three-stated for half- and full-duplex interfaces. table 26. spi registers for test modes address (hex) bit description 0x0d (7) analog loop-back (6) digital loop-back (5) rx port three-state
AD9865 rev. a | page 44 of 48 pcb design considerations although the AD9865 is a mixed-signal device, the part should be treated as an analog component. the on-chip digital circuitry has been specially designed to minimize the impact of its digital switching noise on the mxfes analog performance. to achieve the best performance, the power, grounding, and layout recommendations in this section should be followed. assembly instructions for the micro-lead frame package can be found in an application note from amkor at: http://www.amkor.com/products/notes_papers/mlf_appnote _0902.pdf. component placement if the three following guidelines of component placement are followed, chances for getting the best performance from the mxfe are greatly increased. first, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the mxfe or analog circuits. second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this keeps the highest frequency return current paths short and prevents them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generously bypassed at each device, which further reduces the high frequency ground currents. the mxfe should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections do not flow in the ground plane under the mxfe. the AD9865 has several pins that are used to decouple sensitive internal nodes. these pins are refio, refb, and reft. the decoupling capacitors connected to these points should have low esr and esl. these capacitors should be placed as close to the mxfe as possible (see figure 75) and be connected directly to the analog ground plane. the resistor connected to the refadj pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling while the AD9865 evaluation board demonstrates a very good power supply distribution and decoupling strategy, it can be further simplified for many applications. the board has four layers: two signal layers, one ground plane, and one power plane. while the power plane on the evaluation board is split into multiple analog and digital subsections, a permissible alternative would be to have avdd and clkvdd share the same analog 3.3 v power plane. a separate analog plane/supply may be allocated to the iamp, if its supply voltage differs from the 3.3 v required by avdd and clkvdd. on the digital side, dvdd and drvdd can share the same 3.3 v digital power plane. this digital power plane brings the current used to power the digital portion of the mxfe and its output drivers. this digital plane should be kept from going underneath the analog components. the analog and digital power planes allocated to the mxfe may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the digital portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads be- tween the voltage source and the respective analog and digital power planes with a low esr, bulk decoupling capacitor on the mxfe side of the ferrite. each of the mxfes supply pins (avdd, clkvdd, dvdd, and drvdd) should also have dedicated low esr, esl decoupling capacitors. the decoupling capacitors should be placed as close to the mxfe supply pins as possible. ground planes the AD9865 evaluation board uses a single serrated ground plane to help prevent any high frequency digital ground currents from coupling over to the analog portion of the ground plane. the digital currents affiliated with the high speed data bus interface (pin 1 to pin 16) have the highest potential of generating problematic high frequency noise. a ground serration that contains these currents should reduce the effects of this potential noise source. the ground plane directly underneath the mxfe should be continuous and uniform. the 64-lead lfcsp package is designed to provide excellent thermal conductivity. this is partly achieved by incorporating an exposed die paddle on the bottom surface of the package. however, to take full advantage of this feature, the pcb must have features to effectively conduct heat away from the package. this can be achieved by incorporating thermal pad and thermal vias on the pcb. while a thermal pad provides a solderable surface on the top surface of the pcb (to solder the package die paddle on the board), thermal vias are needed to provide a thermal path to inner and/or bottom layers of the pcb to remove the heat. lastly, all ground connections should be made as short as possible. this results in the lowest impedance return paths and the quietest ground connections. signal routing the digital rx and tx signal paths should be kept as short as possible. also, the impedance of these traces should have a controlled characteristic impedance of about 50 ? . this prevents poor signal integrity and the high currents that can
AD9865 rev. a | page 45 of 48 occur during undershoot or overshoot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, series termination resistors (33 ? to 47 ?) should be placed close to all digital signal sources. it is a good idea to series-terminate all clock signals at their source, regardless of trace length. the receive rx+ and rx? signals are the most sensitive signals on the entire board. careful routing of these signals is essential for good receive path performance. the rx+ and rx? signals form a differential pair and should be routed together as a pair. by keeping the traces adjacent to each other, noise coupled onto the signals appears as common mode and is largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe further reduces the possibility of noise corrupting these signals.
AD9865 rev. a | page 46 of 48 evaluation board an evaluation board is available for the AD9865 and ad9866. the digital interface to the evaluation board can be configured for a half- or full-duplex interface. two 40-pin and one 26-pin male right angle headers (0.100 inches) provide easy interfacing to test equipment such as digital data capture boards, pattern generators, or custom digital evaluation boards (fpga, dsp, or asic). the reference clock source can originate from an exter- nal generator, crystal oscillator, or crystal. software and an interface cable are included to allow for programming of the spi registers via a pc. the analog interface on the evaluation board provides a full analog front-end reference design for power line applications. it includes a power line socket, line transformer, protection diodes, and passive filtering components. an auxiliary path allows independent monitoring of the ac power line. the evaluation board allows complete optimization of power line reference designs based around the AD9865 or ad9866. alternatively, the evaluation board allows independent evalua- tion of the txdac, iamp, and rx paths via sma connectors. the iamp can be easily configured for a voltage or current mode interface via jumper settings. the txdacs performance can be evaluated directly or via an optional dual op amp driver stage. the rx path includes a transformer and termination resistor allowing a calibrated differential input signal to be injected into its front end. the analog devices, inc. website offers more information on the AD9865/ad9866 evaluation board .
AD9865 rev. a | page 47 of 48 outline dimensions * compliant to jedec standards mo-220-vmmd except for exposed pad dimension pin 1 indicator top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.45 0.40 0.35 0.30 0.25 0.18 7.50 ref 0.60 max 0.60 max 7.25 7.10 sq* 6.95 pin 1 indicator 0.25 min 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane exposed pad (b o t t o m view) f i gure 85. 6 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e (lfcs p ) [c p - 6 4 - 3 ] di me nsio ns sho w n i n mi ll im e t e r s ordering guide model t e mper a t ur e r a nge p a ck age descri ption p a ck age o p tion AD9865bcp ?40c to +85c 64-l e ad lfcsp cp -64-3 AD9865bcprl ?40c to +85c 64-l e ad lfcsp cp -64-3 AD9865bcp z 1 ?40c to +85c 64-l e ad lfcsp cp -64-3 AD9865bcp zrl 1 ?40c to +85c 64-l e ad lfcsp cp -64-3 a d 9 8 6 5 c h i p s d i e AD9865-eb e v alua tion boar d 1 z = pb-free part.
AD9865 rev. a | page 48 of 48 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c04493C0 C 11/04(a)

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